US 2019/0056990 A1Published application

Dynamic link error protection in memory systems

AssigneeQUALCOMM Incorporated

InventorsJungwon SUH, Alain ARTIERI, Dexter Tamio CHUN, Deepti Vijayalakshmi SRIRAMAGIRI

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Abstract

Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

Claims33

Dependent claims

An apparatus, comprising:

a memory device configured to communicate with a host over a link,
wherein the memory device comprises:
a plurality of memory cells;
and
a memory link interface configured to
receive a READ command from the host over the link, retrieve READ DATA from the plurality of memory cells, and provide the READ DATA to the host over the link in accordance with an applied link protection mode in response to the READ command, or
receive a WRITE command from the host over the link, receive WRITE DATA from the host over the link, and store the WRITE DATA to the plurality of memory cells in accordance with the applied link protection mode in response to the WRITE command, and
wherein the memory device is configured to
implement a plurality of link protection modes including a first link protection mode and a second link protection mode, wherein the link protection modes are applied to protect at different levels of protection the READ DATA or the WRITE DATA transmitted over the link from errors, and
change from applying the first link protection mode to applying the second link protection mode in response to a link protection mode change notification received from the host.

7 more elements

An apparatus, comprising:

a host configured to communicate with a memory device over a link,
wherein the host comprises:
a host link interface configured to interface with the link;
and
a memory controller configured to communicate with the memory device through the host link interface,
wherein the memory controller is configured to
issue a READ command to the memory device over the link, receive READ DATA from the memory device over the link in accordance with an applied link protection mode upon issuing the READ command, or
issue a WRITE command to the memory device over the link, and provide WRITE DATA to the memory device over the link in accordance with the applied link protection mode upon issuing the WRITE command, and
wherein the host is configured to
implement a plurality of link protection modes including a first link protection mode and a second link protection mode, wherein the link protection modes are applied to protect at different levels of protection the READ DATA or the WRITE DATA transmitted over the link from errors, and
change from applying the first link protection mode to applying the second link protection mode in response to a link speed change.

8 more elements

A method of an apparatus, the apparatus comprising a host and a memory device configured to communication with each other over a link, the method comprising:

changing the apparatus from applying a first link protection mode to applying a second link protection mode in response to a link speed change;
and
issuing a READ command by the host to the memory device over the link, and providing READ DATA by the memory device to the host over the link in accordance with an applied link protection mode in response to the READ command, or
issuing a WRITE command by the host to the memory device over the link, and providing WRITE DATA by the host to the memory device over the link in accordance with the applied link protection mode upon issuing the WRITE command,
wherein the apparatus is configured to implement a plurality of link protection modes including the first and second link protection modes, and
wherein the link protection modes are applied to protect at different levels of protection the READ DATA or the WRITE DATA transmitted over the link from errors.

3 more elements

An apparatus, comprising:

a host and a memory device configured to communicate with each other over a link,
wherein the memory device comprises:
a plurality of memory cells;
and
means for receiving a READ command from the host over the link, means for retrieving READ DATA from the plurality of memory cells in response to the READ command, and means for providing the READ DATA to the host over the link in accordance with an applied link protection mode in response to the READ command, or
means for receiving a WRITE command from the host over the link,
means for receiving WRITE DATA from the host over the link in response to the WRITE command, and means for storing the WRITE DATA to the plurality of memory cells in accordance with the applied link protection mode in response to the WRITE command,
wherein the host comprises:
means for issuing the READ command to the memory device over the link, and means for receiving the READ DATA from the memory device over the link upon issuing the READ command, or
means for issuing the WRITE command to the memory device over the link, and means for providing the WRITE DATA to the memory device over the link in accordance with the applied link protection mode upon issuing the WRITE command, and
wherein the apparatus is configured to
implement a plurality of link protection modes including a first link protection mode and a second link protection mode, wherein the link protection modes are applied to protect at different levels of protection the READ DATA or the WRITE DATA transmitted over the link from errors, and
change from applying the first link protection mode to applying the second link protection mode in response to a link speed change.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/682,533Filed 21 Aug 2017
Published: 21 Feb 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
G06F 3/0619
Improving the reliability of storage systems: in relation to data integrity, e.g. data losses, bit errors
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/068
Single storage device: hybrid storage device