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US 2019/0056941 A1Published application
Reconfigurable microprocessor hardware architecture
OwnerXiaolin Wang, Qian Wuinventors
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OwnerXiaolin Wang, Qian Wuinventors
Estimating the term…
A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, Time Fields are added to the instruction format for all programming units that specify the number of clock cycles for which only one fetched and decoded instruction will be executed.
A reconfigurable and programmable multi-core processor architecture comprising at least one programmable unit that can execute Time Field instructions, wherein each Time Field instruction includes a Time Field opcode that specifies a number of clock cycles during which only a single fetch and decode of an instruction will be performed, followed by repeated executions of the instruction by functional units of the programmable unit.
A method, performed by a reconfigurable and programmable multi-core processor architecture comprising at least one programmable unit, of repeatedly performing a fetched and decoded instruction, the method comprising:
Dependencies are inferred from the claim text.