US 2019/0056915 A1Published application

Memristor based logic gate

AssigneeOxford Brookes University

InventorsABUSALEH MUHAMMAD JABIR, XIAOHAN YANG, ADEDOTUN ADEDEJI ADEYEMO

Life of this patent

Estimating the term…

Loading patent…

Abstract

A logic gate includes first and second inputs, first through fourth memristors each having a positive terminal and a negative terminal, and first and second outputs. The memristors are connected in a bridge arrangement: the negative terminal of the first memristor and the positive terminal of the second memristor are connected to the first input; the negative terminal of the third memristor and the positive terminal of the fourth memristor are connected to the second input; the negative terminal of the second memristor and the negative terminal of the fourth memristor are connected to the first output; and the positive terminal of the first memristor and the positive terminal of the third memristor are connected to the second output. A voltage of at least one of the outputs, or the voltage difference between the outputs, corresponds to the result of a logic operation relative to voltages applied to the inputs.

Claims11

Dependent claims

A logic gate comprising:

a first input and a second input;
a first memristor, a second memristor, a third memristor, and a fourth memristor, each of the memristors having a positive terminal and a negative terminal;
and
a first output and a second output,
wherein the negative terminal of the first memristor and the positive terminal of the second memristor are connected in common to the first input,
wherein the negative terminal of the third memristor and the positive terminal of the fourth memristor are connected in common to the second input,
wherein the negative terminal of the second memristor and the negative terminal of the fourth memristor are connected in common to the first output,
wherein the positive terminal of the first memristor and the positive terminal of the third memristor are connected in common to the second output, and
wherein, in use, a voltage of at least one of the outputs, or a voltage difference between the first and second outputs, corresponds to a result of a logic operation relative to voltages applied to the first and second inputs.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/079,160Filed 20 Feb 2017
Priority: GB 1603089.223 Feb 2016
Published: 21 Feb 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 7/501
Adding; Subtracting: half or full adders, i.e. basic adder cells for one denomination
G11C 13/0007
Using resistive RAM [RRAM] elements: comprising metal oxide memory material, e.g. perovskites
H03K 19/017509
Coupling arrangements; Interface arrangements: interface arrangements
H03K 19/173
Using specified components: using elementary logic circuits as components