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US 2019/0056880 A1Published application
Method for maximizing frequency while checking data integrity on a physical interface bus
AssigneeWestern Digital Technologies, Inc.
InventorsYonatan TZAFRIR, Mordekhay ZEHAVI, Mahmud ASFUR
Life of this patent
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Abstract
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
Claims26
A method comprising:
- in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
- performing, by the controller, a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern;
- performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern;
- and
- changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
2 more elements
A data storage device, comprising:
- a controller and a memory, wherein the controller includes a host interface and a memory interface,
- the controller configured to perform a first operation on the memory through the memory interface at a first frequency of a timing circuit associated with the host interface to determine a first data pattern,
- the controller further configured to perform a read operation on the memory through the memory interface at a second frequency of the timing circuit to determine a second data pattern;
- and
- an interface timing adjustment engine configured to change the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
2 more elements
A data storage device, comprising:
- means for perform a first operation on the memory through the memory interface at a first frequency associated with a host interface to determine a first data pattern;
- means for performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern;
- and
- means for changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
1 more element
A method comprising:
- in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
- (a) writing, by the controller, a write data pattern to the memory through the memory interface at a first frequency associated with the host;
- (b) reading a read data pattern from the memory through the memory interface at a lower frequency having an associated risk of a setup/hold violation that is below a predetermined probability;
- (c) comparing the write data pattern to the read data pattern;
- (d) either:
- responsive to the write data pattern being equal to the read data pattern according to the comparison, increasing the first frequency by a predetermined amount;
- or
- responsive to the write data pattern not being equal to the read data pattern according to the comparison, decreasing the first frequency by a predetermined amount;
- and
- (e) repeating (a)-(c).
7 more elements
A method comprising:
- in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
- (a) reading, by the controller, a first read data pattern from the memory through the memory interface at a low frequency having an associated risk of a setup/hold violation that is below a predetermined probability;
- (b) reading a second read data pattern from the memory through the memory interface at a second frequency higher than the low frequency associated with the host;
- (c) comparing the first read data pattern to the second read data pattern;
- (d) either:
- responsive to the first read data pattern being equal to the second read data pattern according to the comparison, increasing the second frequency by a predetermined amount;
- or
- responsive to the first read data pattern not being equal to the second read data pattern according to the comparison, decreasing the second frequency by a predetermined amount;
- and
- (e) repeating (a)-(c).
7 more elements
Dependencies are inferred from the claim text.