Circuit structures to resolve random testability
AssigneeInternational Business Machines Corporation
InventorsRaghu G. GopalaKrishnaSetty, Mary P. Kusko, Spencer K. Millican
Life of this patent
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Abstract
Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.
Claims13
-6. (canceled)
A system for using circuit structures for resolving random testability, the system comprising:
- a storage medium, the storage medium being coupled to a processor;
- the processor configured to:
- analyze logic structures of a circuit design;
- identify the logic structures of the circuit design that are random resistant structures;
- replace the identified logic structures with random testable structures;
- and
- perform a test of the circuit design including the random testable structures.
A computer program product for using circuit structures for resolving random testability, the computer program product comprising:
- a computer readable storage medium having stored thereon first program instructions executable by a processor to cause the processor to:
- analyze logic structures of a circuit design;
- identify the logic structures of the circuit design that are random resistant structures;
- replace the identified logic structures with random testable structures;
- and
- perform a test of the circuit design including the random testable structures.
Dependencies are inferred from the claim text.