Encapsulated microelectromechanical structure

A method of fabricating a microelectromechanical system (MEMS) device, the method comprising:

• forming within a semiconductor layer of a semiconductor-on-insulator (SOI) wafer:
• a cavity with a MEMS resonator therein,
• a first electrically conductive feature functionally coupled to the MEMS resonator and exposed at a first surface of the semiconductor layer, and
• an insulating region exposed at the first surface of the semiconductor layer adjacent the first electrically conductive feature;
• bonding a semiconductor cover wafer to the first surface of the semiconductor layer of the SOI wafer to hermetically seal the MEMS resonator within the cavity;
• and
• forming within the semiconductor cover wafer a second electrically conductive feature that extends through the semiconductor cover wafer to contact the first electrically conductive feature, including forming an isolation trench that extends through the semiconductor cover wafer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features from a bulk region of the semiconductor cover wafer.

A microelectromechanical system (MEMS) device comprising:

• an oxide layer disposed between first and second semiconductor layers, the first semiconductor layer having formed therein:
• a cavity,
• a MEMS resonator within the cavity,
• a first electrically conductive feature functionally coupled to the MEMS resonator and exposed at a surface of the first semiconductor layer, and
• an insulating region exposed at the surface of the first semiconductor layer adjacent the first electrically conductive feature;
• a semiconductor cover layer bonded to the surface of the first semiconductor layer to hermetically seal the MEMS resonator within the cavity, the semiconductor cover layer having formed therein (i) a second electrically conductive feature that extends through the semiconductor cover layer to contact the first electrically conductive feature, and (ii) an isolation trench that extends through the semiconductor cover layer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features from a bulk region of the semiconductor cover layer.