System, method, and apparatus for sris mode selection for pcie
AssigneeIntel Corporation
InventorsDavid J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
Life of this patent
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Abstract
Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
Claims26
A method for operating a downstream port of an upstream component connected to one or more downstream components across a Peripheral Component Interconnect Express (PCIe)-compliant link, the method comprising:
- determining that the downstream port supports one or more Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode selection mechanisms;
- determining a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link;
- setting an SRIS mode in the downstream port;
- and
- transmitting data across the link from the downstream port using the determined system clock configuration.
A computer program product tangibly embodied on non-transitory computer-readable media, the computer program product comprising instructions that when executed cause logic embodied on a root port controller compliant with a Peripheral Component Interconnect Express (PCIe) protocol to:
- determine that a downstream port associated with an upstream component that is in communication with the root port controller supports one or more Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode selection mechanisms;
- determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by a PCIe-compliant link;
- set an SRIS mode in the downstream port;
- and
- transmit data across the PCIe-compliant link from the downstream port using the determined system clock configuration.
A computing system comprising:
- a root port controller compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the root port comprising a downstream port;
- the downstream port comprising logic implemented at least partially in hardware, the logic to:
- determine that the downstream port supports one or more Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode selection mechanisms;
- determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by a PCIe-compliant link;
- set an SRIS mode in the downstream port;
- and
- transmit data across the link from the downstream port using the determined system clock configuration.
Dependencies are inferred from the claim text.