Integrated controller for motion control and motor control

An integrated controller for motion control and motor control, comprising:

• a first processor configured to run an operating system and at least perform motion control, wherein the motion control comprises calculating set values of kinematic pairs of a controlled object at each moment;
• a second processor configured to at least perform motor control and normally not run the operating system, wherein the motor control comprises controlling movement of motors according to the set values, which at least comprises any one or a combination of motor current loop control, motor speed loop control, and motor position loop control;
• a cache coupled to the first processor and the second processor;
• a shared memory, which is a dedicated cacheable memory block with fixed address specified by the operating system;
• a programmable logic device coupled to the second processor and configured to perform the motor control in conjunction with the second processor;
• wherein,
• the shared memory maps onto the cache;
• the first processor and the second processor are configured to share the shared memory and accordingly perform data transmission via the cache in the periods of motion control and motor control;
• the first processor, the second processor and the cache are integrated in a same chip.

An integrated controller for motion control and motor control, comprising:

• a first processor configured to run an operating system and at least perform motion control, wherein the motion control comprises calculating set values of kinematic pairs of a controlled object at each moment;
• a second processor configured to at least perform motor control and normally not run the operating system, wherein the motor control comprises controlling movement of motors according to the set values, which at least comprises any one or a combination of motor current loop control, motor speed loop control, and motor position loop control;
• a cache coupled to the first processor and the second processor;
• a shared memory, which is a dedicated cacheable memory block with fixed address specified by the operating system;
• a programmable logic device coupled to the second processor and configured to perform the motor control in conjunction with the second processor;
• wherein, the shared memory maps onto the cache;
• the first processor and the second processor are configured to share the shared memory and accordingly perform data transmission via the cache in the periods of motion control and motor control;
• the first processor, the second processor, the cache and the programmable logic device are integrated in a same chip.