Serializer, data transmitting circuit, semiconductor apparatus and system including the same
AssigneeSK hynix Inc.
InventorHyun Bae LEE
Life of this patent
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Abstract
A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.
Claims21
A serializer comprising:
- a pre-buffer stage configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively;
- and
- a main buffer stage configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively,
- wherein the plurality of pre-clock signals have phase differences from the plurality of main clock signals, respectively.
A serializer comprising:
- a pre-buffer stage configured to generate a first delayed signal by buffering a first signal in synchronization with a first clock signal, and generate a second delayed signal by buffering a second signal in synchronization with a second clock signal;
- and
- a main buffer stage configured to generate an output signal by buffering the first delayed signal in synchronization with the second clock signal.
A serializer comprising:
- a pre-buffer stage configured to generate first to fourth delayed signals by buffering first to fourth signals in synchronization with first to fourth clock signals, respectively;
- and
- a main buffer stage configured to generate an output signal by buffering the first to fourth delayed signals in synchronization with the first to fourth clock signals, respectively.
A data transmission circuit comprising:
- a pipe latch circuit configured to output first to fourth data by arranging a plurality of internal data groups;
- a pre-buffer stage configured to generate first to fourth delayed data by buffering the first to fourth data in synchronization with first to fourth clock signals, respectively;
- and
- a main buffer stage configured to generate an output data by buffering the first to fourth delayed data in synchronization with the first to fourth clock signals, respectively.
Dependencies are inferred from the claim text.