Physical layer circuit, clock recovery circuit and calibration method of frequency offset
AssigneeALi Corporation
InventorLin LI
Life of this patent
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AssigneeALi Corporation
InventorLin LI
Estimating the term…
A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.
A clock recovery circuit comprising:
A physical layer circuit comprising:
A calibration method of frequency offset applied to a physical layer circuit of a receiver, the calibration method of frequency offset comprising steps of:
Dependencies are inferred from the claim text.