Adaptive-snr ultra-low-power ultra-low-noise microphone

An SNR monitor comprising:

• a first input connected to a third low-pass-filter output;
• a second input connected to a fourth low-pass-filter output;
• one of:
• a third analog input, and a third digital input, that determines the required SNR:
• a first output connected to a control input of a controlled Vref;
• and
• an optional second output connected to a control input of an optional controlled charge pump.

A microphone comprising:

• a transistor comprising at least one of a JFET and MOSFET transistor;
• an impedance network, wherein a first input terminal of the impedance network is connected to a gate terminal of the transistor;
• a source resistor, wherein a first terminal of the source resistor is connected to a source terminal of the transistor, and a second terminal of the source resistor is connected to a ground terminal;
• a bypass capacitor (CS) connected in parallel to the source resistor;
• a load resistor (RD), wherein a first terminal of the load resistor is connected to a drain terminal of the transistor;
• a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• an op-amplifier, wherein
• a first input terminal of the op-amplifier is connected to the source terminal of the transistor through a bi-directional low-pass-filter transistor;
• a second input terminal of the op-amplifier is connected to a controlled reference voltage Vref;
• a first power supply of the op-amplifier terminal is connected to the inverted voltage;
• a second supply terminal of the op-amplifier is connected to the main supply voltage;
• and
• an output terminal of the op-amplifier is connected to a second terminal of the input impedance network through a second low pass filter;
• and
• an input source comprising:
• a MEMS capacitor, wherein a first terminal of the MEMS capacitor is connected to ground, and a second terminal of the MEMS capacitor is connected to a first terminal of a MEMS bias network;
• the MEMS bias network, wherein a second terminal of the MEMS bias network is connected to a bias voltage VBB;
• and
• a coupling capacitor, wherein a first terminal of the coupling capacitor is connected to the second terminal of the MEMS capacitor, and with a second terminal of the coupling capacitor is connected to the gate terminal of the transistor;
• an ultra-low-power envelope/energy detector connected to drain terminal of the transistor via a coupling capacitor;
• a third low-pass-filter connected to the output of the ultra-low-power envelope/energy detector;
• and
• a fourth low-pass-filter connected to the output of the ultra-low-power envelope/energy detector.

A microphone comprising:

• a transistor comprising at least one of a JFET and MOSFET transistor;
• an impedance network, wherein a first input terminal of the impedance network is connected to a gate terminal of the transistor;
• a source resistor, wherein a first terminal of the source resistor is connected to a source terminal of the transistor, and a second terminal of the source resistor is connected to a ground terminal;
• a bypass capacitor (CS) connected in parallel to the source resistor;
• a load resistor (RD), wherein a first terminal of the load resistor is connected to a drain terminal of the transistor;
• a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• the op-amplifier, wherein
• a first input terminal of the op-amplifier is connected to a controlled reference voltage connected to first output terminal of a differential bi-directional low-pass-filter, wherein a first input terminal of the differential bi-directional low-pass-filter is connected to a second terminal of the load resistor;
• a second input terminal of the op-amplifier is connected to a second output terminal of a differential bi-directional low-pass-filter, wherein a second input terminal of the differential bi-directional low-pass-filter is connected to the first terminal of the load resistor;
• a first power supply of the op-amplifier terminal is connected to the inverted voltage;
• a second supply terminal of the op-amplifier is connected to the main supply voltage;
• and
• an output terminal of the op-amplifier is connected to a second terminal of the input impedance network through a second low pass filter;
• an input electrets capacitor source connected in parallel to the input impedance network;
• an ultra-low-power envelope/energy detector connected to drain terminal of the transistor via a coupling capacitor;
• a third low-pass-filter connected to the output of the ultra-low-power envelope/energy detector;
• and
• a fourth low-pass-filter connected to the output of the ultra-low-power envelope/energy detector.

A microphone comprising:

• a transistor comprising at least one of a JFET and MOSFET transistor;
• an impedance network, wherein a first input terminal of the impedance network is connected to a gate terminal of the transistor;
• a source resistor, wherein a first terminal of the source resistor is connected to a source terminal of the transistor, and a second terminal of the source resistor is connected to a ground terminal;
• a bypass capacitor (CS) connected in parallel to the source resistor;
• a load resistor (RD), wherein a first terminal of the load resistor is connected to a drain terminal of the transistor;
• a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• an op-amplifier, wherein
• a first input terminal of the op-amplifier is connected to a controlled reference voltage connected to first output terminal of a differential bi-directional low-pass-filter, wherein a first input terminal of the differential bi-directional low-pass-filter is connected to a second terminal of the load resistor;
• a second input terminal of the op-amplifier is connected to a second output terminal of a differential bi-directional low-pass-filter, wherein a second input terminal of the differential bi-directional low-pass-filter is connected to the first terminal of the load resistor;
• a first power supply of the op-amplifier terminal is connected to the inverted voltage;
• a second supply terminal of the op-amplifier is connected to the main supply voltage;
• and
• an output terminal of the op-amplifier is connected to a second terminal of the input impedance network through a second low pass filter;
• and
• an input source comprising:
• a MEMS capacitor, wherein a first terminal of the MEMS capacitor is connected to ground and a second terminal of the MEMS capacitor is connected to a first terminal of a MEMS bias network;
• a MEMS bias network connected with it second terminal to a bias voltage VBB;
• and
• the MEMS bias network, wherein a second terminal of the MEMS bias network is connected to a bias voltage VBB;
• and
• a coupling capacitor, wherein a first terminal of the coupling capacitor is connected to the second terminal of the MEMS capacitor, and with a second terminal of the coupling capacitor is connected to the gate terminal of the transistor.

A method for sensing an acoustic signal, the method comprising:

• connecting a first input terminal of an impedance network to a gate terminal of a transistor comprising at least one of a JFET and MOSFET transistor;
• connecting a first terminal of a source resistor to a source terminal of the transistor, and a second terminal of the source resistor to a ground terminal;
• connecting a bypass capacitor (CS) in parallel with the source resistor;
• connecting a first terminal of a load resistor (RD) to a drain terminal of the transistor;
• connecting a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• connecting a first input terminal of the op-amplifier to the source terminal of the transistor through a bi-directional low-pass-filter transistor;
• connecting a second input terminal of the op-amplifier to a controlled reference voltage Vref;
• connecting a first power supply terminal of the op-amplifier to the inverted voltage;
• connecting a second supply terminal of the op-amplifier to the main supply voltage;
• and
• connecting an output terminal of the op-amplifier to a second terminal of the input impedance network through a second low pass filter;
• and
• connecting an input electrets capacitor source in parallel with the input impedance network;
• connecting an ultra-low-power envelope/energy detector to drain terminal D of the transistor via coupling capacitor;
• connecting a third low-pass-filter to the output of the ultra-low-power envelope/energy detector;
• and
• connecting a fourth low-pass-filter to the output of the ultra-low-power envelope/energy detector.

An SNR monitor comprising:

• a first input connected to a third low-pass-filter output;
• a second input connected to a fourth low-pass-filter output;
• one of:
• a third analog input, and a third digital input, that determines the required SNR:
• a first output connected to a control input of a controlled Vref;
• and
• an optional second output connected to a control input of an optional controlled charge pump.

A method for sensing an acoustic signal, the method comprising:

• connecting a first input terminal of an impedance network to a gate terminal of a transistor comprising at least one of a JFET and MOSFET transistor;
• connecting a first terminal of a source resistor to a source terminal of the transistor, and a second terminal of the source resistor to a ground terminal;
• connecting a bypass capacitor (CS) in parallel with the source resistor;
• connecting a first terminal of a load resistor (RD) to a drain terminal of the transistor;
• connecting a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• connecting a first input terminal of the op-amplifier to the source terminal of the transistor through a bi-directional low-pass-filter transistor;
• connecting a second input terminal of the op-amplifier to a controlled reference voltage Vref;
• connecting a first power supply terminal of the op-amplifier to the inverted voltage;
• connecting a second supply terminal of the op-amplifier to the main supply voltage;
• and
• connecting an output terminal of the op-amplifier to a second terminal of the input impedance network through a second low pass filter;
• and
• connecting an input source comprising:
• a MEMS capacitor, wherein a first terminal of the MEMS capacitor is connected to ground, and a second terminal of the MEMS capacitor is connected to a first terminal of a MEMS bias network;
• the MEMS bias network, wherein a second terminal of the MEMS bias network is connected to a bias voltage VBB;
• and
• a coupling capacitor, wherein a first terminal of the coupling capacitor is connected to the second terminal of the MEMS capacitor, and with a second terminal of the coupling capacitor is connected to the gate terminal of the transistor.
• connecting an ultra-low-power envelope/energy detector to drain terminal of the transistor via a coupling capacitor;
• connecting a third low-pass-filter to the output of the ultra-low-power envelope/energy detector;
• and
• connecting a fourth low-pass-filter to the output of the ultra-low-power envelope/energy detector;

A method for sensing an acoustic signal, the method comprising:

• connecting a first input terminal of an impedance network to a gate terminal of a transistor comprising at least one of a JFET and MOSFET transistor;
• connecting a first terminal of a source resistor to a source terminal of the transistor, and a second terminal of the source resistor to a ground terminal;
• connecting a bypass capacitor (CS) in parallel with the source resistor;
• connecting a first terminal of a load resistor (RD) to a drain terminal of the transistor;
• connecting a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• connecting a first input terminal of the op-amplifier to a controlled reference voltage connected to first output terminal of a differential bi-directional low-pass-filter;
• connecting a first input terminal of the differential bi-directional low-pass-filter to a second terminal of the load resistor;
• connecting a second input terminal of the op-amplifier to a second output terminal of a differential bi-directional low-pass-filter;
• connecting a second input terminal of the differential bi-directional low-pass-filter to the first terminal of the load resistor;
• connecting a first power supply of the op-amplifier terminal to the inverted voltage;
• connecting a second supply terminal of the op-amplifier to the main supply voltage;
• connecting an output terminal of the op-amplifier to a second terminal of the input impedance network through a second low pass filter;
• connecting an input electrets capacitor source in parallel to the input impedance network;
• connecting an ultra-low-power envelope/energy detector to drain terminal D of the transistor via a coupling capacitor;
• connecting a third low-pass-filter to the output of the ultra-low-power envelope/energy detector;
• and
• connecting a fourth low-pass-filter connected to the output of the ultra-low-power envelope/energy detector.

A method for sensing an acoustic signal, the method comprising:

• connecting a first input terminal of an impedance network to a gate terminal of a transistor comprising at least one of a JFET and MOSFET transistor;
• connecting a first terminal of a source resistor to a source terminal of the transistor, and a second terminal of the source resistor to a ground terminal;
• connecting a bypass capacitor (CS) in parallel with the source resistor;
• connecting a first terminal of a load resistor (RD) to a drain terminal of the transistor;
• connecting a charge pump generating a low voltage power supply VCC_LOW and an inverted voltage −VEE, wherein the low voltage is connected to a second terminal of the load resistor, and the inverted voltage −VEE is connected to a first power supply node of an op-amplifier;
• connecting a first input terminal of the op-amplifier to a controlled reference voltage connected to first output terminal of a differential bi-directional low-pass-filter;
• connecting a first input terminal of the differential bi-directional low-pass-filter to a second terminal of the load resistor;
• connecting a second input terminal of the op-amplifier to a second output terminal of a differential bi-directional low-pass-filter;
• connecting a second input terminal of the differential bi-directional low-pass-filter to the first terminal of the load resistor;
• connecting a first power supply of the op-amplifier terminal to the inverted voltage;
• connecting a second supply terminal of the op-amplifier to the main supply voltage;
• connecting an output terminal of the op-amplifier to a second terminal of the input impedance network through a second low pass filter;
• and
• connecting an input source comprising:
• a MEMS capacitor, wherein a first terminal of the MEMS capacitor is connected to ground and a second terminal of the MEMS capacitor is connected to a first terminal of a MEMS bias network;
• a MEMS bias network connected with it second terminal to a bias voltage VBB;
• and
• the MEMS bias network, wherein a second terminal of the MEMS bias network is connected to a bias voltage VBB;
• and
• a coupling capacitor, wherein a first terminal of the coupling capacitor is connected to the second terminal of the MEMS capacitor, and with a second terminal of the coupling capacitor is connected to the gate terminal of the transistor.