Increasing resolution of on-chip timing uncertainty measurements

A method comprising:

• receiving an output from a programmable delay circuit output of a programmable delay circuit on a delay input of a first delay circuit in a set of delay circuits logically coupled in a chain configuration;
• in response to the delay input of the first delay circuit in the set of delay circuits receiving the output from the programmable delay circuit output of the programmable delay circuit, receiving an output from a delay output of each of the delay circuits on a flip-flop input of each of a plurality of flip-flop circuits, wherein the plurality of flip-flop circuits forms tiers of flip-flop circuits;
• transmitting by a clock circuit to each of the tiers of flip-flop circuits a skewed clock signal comprising a programmable delay from a clock output of the clock circuit to a clock input of each flip-flop circuit in the each of the tiers of flip-flop circuits, resulting in skewed clock signals including corresponding programmable delays being transmitted by clock circuits to the tiers of flip-flop circuits respectively;
• and
• in response to receiving the output from the delay output of the each of the delay circuits on the flip-flop input of the each of the plurality of flip-flop circuits and in response to receiving the skewed clock signals from the clock circuits. indicating by the plurality of flip-flop circuits, via flip-flop outputs of the plurality of flip-flop circuits, how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively
• wherein the skewed clock signals have a common frequency, and
• wherein each of the skewed clock signals has a different arrival time (skew) as determined by a corresponding programmable delay.

A method comprising:

• receiving an output from a programmable delay circuit output of a programmable delay circuit on a delay input of a first delay circuit in a set of delay circuits logically coupled in a chain configuration;
• in response to the delay input of the first delay circuit in the set of delay circuits receiving the output from the programmable delay circuit output of the programmable delay circuit, receiving an output from a delay output of each of the delay circuits on a flip-flop input of each of a plurality of flip-flop circuits, where the plurality of flip-flop circuits forms tiers of flip-flop circuits;
• and
• in response to receiving the output from the delay output of the each of the delay circuits on the flip-flop input of the each of the plurality of flip-flop circuits and in response to receiving skewed clock signals from clock circuits on a clock input of each flip-flop circuit in each of the tiers of flip-flop circuits, indicating by the plurality of flip-flop circuits, via flip-flop outputs of the plurality of flip-flop circuits, how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively;
• transmitting by a clock circuit to the each of the tiers of flip-flop circuits a skewed clock signal comprising a programmable delay from a clock output of the clock circuit to a clock input of each flip-flop circuit in the each of the tiers of flip-flop circuits, resulting in skewed clock signals including corresponding programmable delays being transmitted by the clock circuits to the tiers of flip-flop circuits respectively,
• wherein the skewed clock signals have a common frequency, and
• wherein each of the skewed clock signals has a different arrival time (skew) as determined by a corresponding programmable delay.