Square root digit recurrence
AssigneeArm Limited
InventorsJavier Diaz BRUGUERA, David M. RUSSINOFF
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Abstract
A data processing apparatus is provided, for performing a digit-recurrence square root operation on an input value. Receiver circuitry receives a remainder value of a previous iteration of the digit-recurrence square root operation. Comparison circuitry compares most significant bits of the remainder value of the previous iteration with a number of selection constants, in order to output a next digit of a result of the digit-recurrence square root operation. The comparison circuitry compares at most 3 fractional bits of the remainder value of the previous iteration with the plurality of selection constants.
Claims15
A data processing apparatus to perform a digit-recurrence square root operation on an input value, comprising:
- receiver circuitry to receive a remainder value of a previous iteration of said digit-recurrence square root operation;
- and
- comparison circuitry to compare most significant bits of said remainder value of said previous iteration with a plurality of selection constants, to output a next digit of a result of said digit-recurrence square root operation, wherein
- said comparison circuitry compares at most 3 fractional bits of said remainder value of said previous iteration with said plurality of selection constants.
A data processing method for performing a digit-recurrence square root operation on an input value, comprising:
- receiving, by receiver circuitry, a remainder value of a previous iteration of said digit-recurrence square root operation;
- and
- comparing, by comparison circuitry, most significant bits of said remainder value of said previous iteration with a plurality of selection constants, to output a next digit of a result of said digit-recurrence square root operation, wherein
- said comparing compares at most 3 fractional bits of said remainder value of said previous iteration with said plurality of selection constants.
A data processing apparatus to perform a digit-recurrence square root operation on an input value, comprising:
- means for receiving a remainder value of a previous iteration of said digit-recurrence square root operation;
- and
- means for comparing most significant bits of said remainder value of said previous iteration with a plurality of selection constants, for outputting a next digit of a result of said digit-recurrence square root operation, wherein
- said means for comparing compares at most 3 fractional bits of said remainder value of said previous iteration with said plurality of selection constants.
Dependencies are inferred from the claim text.