US 2018/0351582 A1Published application

Adaptive outer code for consistent overprovisioning (op) level

AssigneeSeagate Technology LLC

InventorTimothy Canepa

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Abstract

Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.

Claims20

Dependent claims

An apparatus comprising:

a solid-state non-volatile memory (NVM) having a total user data storage capacity and an overprovisioning (OP) level;
a control circuit configured to write parity data sets to the NVM, each parity data set comprising a plurality of code words and an outer code, each of the plurality of code words comprising a user data payload and an inner code at an inner code rate to detect and correct read errors in the user data payload, the outer code comprising parity data at an outer code rate to detect and correct read errors in the plurality of code words;
and
a code adjustment circuit configured to increase the inner code rate of the inner code of at least one parity data set responsive to a measured parameter associated with the NVM, and to decrease the outer code rate of the outer code of the at least one parity data set responsive to the increase of the inner code rate to maintain the total user data storage capacity at or above a first threshold and to maintain the OP level at or above a second threshold.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 15/610,744Filed 1 Jun 2017
Published: 6 Dec 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H03M 13/2909
Using block codes: product codes
G06F 11/1012
In individual solid state devices: using codes or arrangements adapted for a specific type of error
G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters