Synchronous Clock Generation Using an Interpolator
AssigneeTexas Instruments Incorporated
InventorsSrikanth Manian, Srinivas Theertham, Jagdish Chand, Dinesh Jain
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Abstract
In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
Claims7
A method, comprising:
- receiving a device clock signal;
- generating a synchronization (SYSREF) clock signal at least partially according to the device clock signal;
- generating a shifted clock signal at least partially according to the device clock signal;
- sampling, by a latch, the SYSREF clock signal using the shifted clock signal;
- and
- outputting the sampled SYSREF clock signal.
Dependencies are inferred from the claim text.