Methods and apparatus for sequencing multiply-accumulate operations

A method for operating a specialized processing block, comprising:

• receiving, at a first input, a first signal of a plurality of signals from a sequencer circuit, wherein the plurality of signals are received in a predetermined order;
• receiving second and third signals of the plurality of signals at second and third inputs of the specialized processing block;
• routing, in a first mode, the first and second signals to first and second multiplier input ports of a multiplier to produce a first product;
• and
• routing, in a second mode, the second and third signals to the first and second multiplier input ports to produce a second product, wherein the multiplier has a multiplier output port coupled to an output of the specialized processing block.

A method for operating a sequencer circuit, comprising:

• conveying a clock signal that provides a plurality of trigger events;
• incrementing, by a counter of the sequencer circuit, by a predetermined number that is greater than one at a first trigger event of the plurality of trigger events to produce a counter output;
• computing, by an adder of the sequencer circuit, a sum of first and second signals to produce a read address signal;
• receiving, at a storage circuit of the sequencer circuit, a write data signal, the read address signal, and the counter output;
• storing the write data signal at a first address of the storage circuit at least in part based on the counter output, at a second trigger event of the plurality of trigger events;
• outputting, by the storage circuit, a read data signal from a second address of the storage circuit at least in part based on the read address signal;
• and
• sending the read data signal from the sequencer circuit to an arithmetic circuit.

An integrated circuit, comprising:

• a sequencer circuit including
• a first storage circuit that receives a first read address signal and retrieves a control signal from a first location of the first storage circuit at least in part based on the first read address signal,
• an adder circuit that computes a second read address signal at least in part based on the control signal,
• a counter circuit that increments a counter output signal with a maximum number signal and sends the counter output signal to the adder circuit, and
• a second storage circuit that retrieves a data signal from a second location at least in part based on the second read address signal;
• and
• a multiply-accumulate circuit that computes an output signal by multiplying the data signal with a coefficient signal.