# US 2018/0324379 A1 · Comparator for double ramp analog to digital converter

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- Number: US 2018/0324379 A1
- Document ID: US20180324379A1
- Status: Published application
- Kind: A1
- Application number: 16/035,388
- Filed: 2018-07-13
- Published: 2018-11-08
- Earliest claimed: 2016-09-27
- Assignees: OmniVision Technologies, Inc.
- Applicants: OmniVision Technologies, Inc.
- Inventors: Hiroaki Ebihara; Zheng Yang
- Web page: https://patentgrep.com/patent/US20180324379A1

## CPC

- H03K 5/2481: {with at least one differential stage}
- H04N 25/671: for non-uniformity detection or correction
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A comparator includes a first stage coupled to compare a reference voltage to an image charge voltage signal. The first stage includes first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices to receive the reference voltage and the image charge voltage signal. A first auto-zero switch is between a gate of the first NMOS input transistor and a first node. The first node is between the first NMOS input transistor and the first cascode device. A second auto-zero switch is between a gate of the second NMOS input transistor and a second node. The second node is between the second cascode device and a second PMOS transistor. A voltage difference between the first and second nodes during an auto-zero period reduces an amount of kickback that occurs during an ADC period.

## Claims

### Claim 1

A comparator, comprising:
a first stage coupled to compare a reference voltage to an image charge voltage signal and provide a first output in response, the first stage including:
first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices, wherein gates of the first and second NMOS input transistors are coupled to receive the reference voltage and the image charge voltage signal, respectively;
a first auto-zero switch coupled between the gate of the first NMOS input transistor and a first node, the first node formed between the first NMOS input transistor and the first cascode device; and
a second auto-zero switch coupled between the gate of the second NMOS input transistor and a second node, the second node formed between a second cascode device and a second PMOS transistor, wherein the second node is an output of the first stage,
wherein a voltage difference between the first and second nodes that the first and second NMOS input transistors are coupled to during an auto-zero period of operation of the comparator reduces an amount of kickback that occurs during an ADC period of operation of the comparator.

### Claim 2 (depends on 1)

The comparator of claim 1, further comprising a second stage coupled to receive the first output and provide a second output in response, the second stage including:
a PMOS input transistor coupled to receive the first output at a gate;
a first capacitor coupled to store a second stage reference voltage;
a reference voltage input coupled to the PMOS input transistor at a drain, and further coupled to the first capacitor at a gate; and
a first control switch coupled between the gate of the PMOS input transistor and a third node of the first stage, wherein the third node of the first stage is formed between the first cascode device and a first PMOS transistor, and
wherein the first capacitor is charged to a voltage based on a voltage on the third node of the first stage in response to the first control switch being enabled.

### Claim 3 (depends on 1)

The comparator of claim 1, wherein the first and second cascode devices include an NMOS transistor coupled to a PMOS transistor by their sources and drains, and wherein gates of the NMOS transistors are coupled together, and wherein gates of the PMOS transistors are coupled to receive a first control signal.

### Claim 4 (depends on 3)

The comparator of claim 3, wherein the gates of the NMOS transistors are coupled to a high reference voltage.

### Claim 5 (depends on 3)

The comparator of claim 3, wherein the gates of the NMOS transistors are coupled to a cascode bias voltage through a local sampling circuit, the local sampling circuit controllable to decoupled the gates of the NMOS transistors from the cascode bias voltage during an analog-to-digital operation.

### Claim 6 (depends on 1)

The comparator of claim 1, wherein the first and second cascode devices are coupled to be disabled in response to the comparator having low analog gain.

### Claim 7 (depends on 1)

The comparator of claim 1, wherein the first and second cascode devices are coupled to be enabled in response to the comparator having high analog gain.

### Claim 8

An imaging system, comprising:
an array of pixels to receive image light and generate an image charge voltage signal in response;
readout circuitry coupled to receive the image charge voltage signal from the array of pixels and provide a digital representation of the image charge voltage signal in response, the readout circuitry including a comparator to receive the image charge, compare the image charge voltage signal to a reference voltage, and provide the digital representation of the image charge voltage signal in response, wherein the comparator comprises:
a first stage coupled to receive the image charge and the reference voltage and provide a first output in response; and
a second stage coupled to receive the first output and provide the digital representation of the image charge voltage signal in response, the second stage comprising:
an input coupled to receive the first output;
a first capacitor coupled to store a second stage reference voltage;
a reference voltage input coupled to the input, and further coupled to the first capacitor at a gate; and
a first control switch coupled between the input and a third node of the first stage, and
wherein the first capacitor is charged to a voltage based on a voltage on the third node of the first stage in response to the first control switch being enabled.

### Claim 9 (depends on 8)

The imaging system of claim 8, wherein the first stage comprises:
first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices, wherein gates of the first and second NMOS input transistors are coupled to receive the reference voltage and the image charge voltage signal, respectively;
a first auto-zero switch coupled between the gate of the first NMOS input transistor and a first node, the first node formed between the first NMOS input transistor and the first cascode device; and
a second auto-zero switch coupled between the gate of the second NMOS input transistor and a second node, the second node formed between a second cascode device and a second PMOS transistor, wherein the second node is an output of the first stage.

### Claim 10 (depends on 9)

The imaging system of claim 9, wherein a voltage difference between the first and second nodes that the first and second NMOS input transistors are coupled to during an auto-zero period of operation of the comparator reduces an amount of kickback that occurs during an ADC period of operation of the comparator.

### Claim 11 (depends on 8)

The imaging system of claim 8, further comprising a ramp generator coupled to provide the reference voltage.

### Claim 12 (depends on 8)

The imaging system of claim 8, wherein the second stage input is a PMOS transistor coupled to receive the first output and coupled to the third node at a gate.

### Claim 13 (depends on 12)

The imaging system of claim 12, wherein the second stage further includes first and second control switches coupled to control the coupling of the gate of the PMOS transistor to receive the first output and to the third node, respectively.