# US 2018/0323968 A1 · Physically Unclonable Function Circuits and Methods of Performing Key Enrollment in Physically Unclonable Function Circuits

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- Number: US 2018/0323968 A1
- Document ID: US20180323968A1
- Status: Published application
- Kind: A1
- Application number: 16/023,626
- Filed: 2018-06-29
- Published: 2018-11-08
- Earliest claimed: 2014-11-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yong Ki Lee; Yongsoo Kim; Bohdan Karpinskyy; Yunhyeok Choi
- Web page: https://patentgrep.com/patent/US20180323968A1

## CPC

- H04L 9/088: {Usage controlling of secret information, e.g. techniques for restricting cryptographic keys to pre-authorized uses, different access levels, validity of crypto-period, different key- or password length, or different strong and weak cryptographic algorithms (network architectures or network communication protocols for using time-dependent keys in a packet data network H04L63/068)}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H04L 2209/046: of operations, operands or results of the operations
- H04L 2209/34: Encoding or coding, e.g. Huffman coding or error correction
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY

## Abstract

A key enrollment method of a physically unclonable function (PUF) circuit including a plurality of PUF cells includes receiving a first level key from PUF cells, performing bit encoding on the first level key using a bit coding table based on Hamming weights of a plurality of bits in the first level key to generate a second level key, storing first helper data associated with the second level key in a non-volatile memory, performing block encoding on the second level key using an error correction code to generate a third level key, and storing second helper data associated with the third level key in the non-volatile memory.

## Claims

### Claim 1

A method of storing secure key information into a nonvolatile memory device, the method comprising:
generating a plurality of first key values from a source of the secure key information, each of the plurality of first key values including a plurality of first bits;
performing bit-encoding on each of the plurality of first key values based on a hamming weight of the plurality of first bits in the each of the plurality of first key values, to generate a plurality of second bits and mask data including a plurality of mask values;
storing first helper data corresponding to the mask data into the nonvolatile memory device;
performing block-encoding on the plurality of second bits using block-based error correction coding to generate a plurality of third bits and second helper data; and
storing the second helper data into the nonvolatile memory device.

### Claim 2 (depends on 1)

The method of claim 1, wherein a logic operation on each of the first key values and corresponding one of the plurality of mask values generates a predetermined value.

### Claim 3 (depends on 2)

The method of claim 2, wherein each of the mask values comprises a plurality of bits, the plurality of bits is same as a number of the first bits of each of the first key value, and
the predetermined value a bit stream of which all bits are one of “1” and “0”.

### Claim 4 (depends on 1)

The method of claim 1, wherein if the hamming weight is even, a corresponding one of the plurality of second bits is a first logic value, and
if hamming weight is odd, the corresponding one of the plurality of second bits is a second logic value.

### Claim 5 (depends on 4)

The method of claim 4, wherein if the corresponding one of the plurality of second bits is the first logic value, corresponding one of the plurality of first key values is the same as corresponding one of the plurality of mask values,
if the corresponding one of the plurality of second bits is the second logic value, corresponding one of the plurality of first key values is a value to which the corresponding one of the plurality of mask values is inverted.

### Claim 6 (depends on 1)

The method of claim 1, wherein a space of the plurality of mask values is a half of a space of the plurality of first key values.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first helper data comprises a plurality of first helper values, each of the plurality of first helper values including at least a part of corresponding one of the plurality of the mask values.

### Claim 8 (depends on 1)

The method of claim 1, the performing block-encoding on the plurality of second bits comprises:
performing the block-encoding on at least part of the plurality of second bits to generate second mask data; and
XORing the second mask data and rest of the plurality of second bits to generate the second helper data.

### Claim 9 (depends on 1)

The method of claim 1, wherein a number of the plurality of second bits is greater than a number of the plurality of third bits.

### Claim 10 (depends on 1)

The method of claim 1, wherein the source of the secure key information is a physically unclonable function (PUF) array including a plurality of PUF cells.

### Claim 11 (depends on 10)

The method of claim 10, wherein the plurality of first key values are generated from the plurality of PUF cells, respectively.

### Claim 12

A method of generating a secure key for an electronic device including a nonvolatile memory, the method comprising:
generating a plurality of first key values, each of the plurality of first key values including a plurality of first bits;
reading a plurality of first helper data values stored in the nonvolatile memory, each of the plurality of first helper data values corresponding to the each of the plurality of first key values;
performing bit error correction operation on the each of the plurality of first key values using the plurality of first helper data values to generate a plurality of second key values;
reading second helper data stored in the nonvolatile memory;
performing block error correction operation on the plurality of second key values using the second helper data to correction an error in the plurality of second key values; and
outputting the plurality of second key values in which the error is corrected as the secure key.

### Claim 13 (depends on 12)

The method of claim 12, wherein the bit error correction operation comprises:
performing a logical operation on the each of the plurality of first key values and each of the plurality of first helper data values; and
performing a majority voting operation on a result of the logical operation to generate the plurality of second key values.

### Claim 14 (depends on 12)

The method of claim 12, wherein the plurality of first key values are generated from a physically unclonable function (PUF) circuit including a plurality of PUF cells.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
transmitting, to an external server, an identification (ID) corresponding to the secure key;
receiving, from the external server, a challenge corresponding to the ID; and
transmitting, in response to the challenge, a response to the external server.

### Claim 16

An electronic device comprising:
a nonvolatile memory;
a secure key source configured to generate a plurality of first key value, each of the plurality of first key value including a plurality of first bits; and
an error correction unit configured to correct errors in each of the plurality of first key values,
wherein the error correction unit comprises:
a bit encoder configured to perform bit encoding on each of the plurality of first key values to generate a plurality of second bits and a plurality of mask values, each of the plurality of second bits corresponding to hamming weight in the each of the plurality of first key values, each of the plurality of mask values corresponding to the each of the plurality of first key values; and
a block encoder configured to perform block encoding on the plurality of second bits using an error correction code to generate a third level key and second helper data, and to output the second helper data to the nonvolatile memory,
wherein a logical operation between one of the plurality of first key values and corresponding one of the mask values generates a predetermined value.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the secure key source comprises a plurality of physically unclonable function (PUF) cells, each of the plurality of PUF cells being based on a transistor threshold voltage, and
the plurality of first key values are generated from the plurality of PUF cells, respectively.

### Claim 18 (depends on 17)

The electronic device of claim 17, wherein a space of the mask values is a half of a space of the plurality of first key values.

### Claim 19 (depends on 17)

The electronic device of claim 17 further comprises:
a cryptographic processing circuit configured to perform an encryption operation or a decryption operation of input data or output data using the third level key.

### Claim 20 (depends on 17)

The electronic device of claim 17, wherein the bit encoder performs the bit encoding without random bits.