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US 2018/0323952 A1Published application
Physical layer circuitry for multi-wire interface
AssigneeM31 Technology Corporation
InventorsChing-Hsiang Chang, Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang
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Abstract
The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).
Claims18
A physical layer circuitry (PHY), comprising:
- four signal pads;
- a four-signal physical medium attachment sublayer (PMA) coupled to the four signal pads, comprising:
- a four-signal termination circuit coupled to the four signal pads;
- a first differential amplifier coupled to a first signal pad and a second signal pad, arranged to receive signals on the first signal pad and the second signal pad and accordingly output a first differential signal;
- a second differential amplifier coupled to the first signal pad and a third signal pad, arranged to signals on the first signal pad and the third signal pad and accordingly output a second differential signal;
- a third differential amplifier coupled to two switches, selectively coupled to the second signal pad and the third pad signal or the third signal pad and a fourth signal pad, arranged to receive signals on the second signal pad and the third signal pad or the third signal pad and the fourth signal pad and accordingly output a third differential signal;
- a first signal processing block coupled to the first differential amplifier, arranged to process the first differential signal when the four-signal PMA is operated in a first PHY mode;
- a second signal processing block coupled to the first, second and third differential amplifiers, arranged to process the first, second and third differential signals when the four-signal PMA is operated in a second PHY mode;
- and
- a third signal processing block coupled to the third differential amplifier, arranged to process the third differential signal when the four-signal PMA is operated in the first PHY mode.
7 more elements
A physical layer circuitry (PHY), comprising:
- six signal pads;
- and
- a six-signal physical medium attachment sublayer (PMA), comprising:
- a six-signal termination circuit coupled to the six signal pads respectively;
- a first differential amplifier coupled to a first signal pad and a second signal pad, arranged to receive signals on the first signal pad and the second signal pad and output a first differential signal;
- a second differential amplifier coupled to the first signal pad and a third signal pad, arranged to receive signals on the first signal pad and the third signal pad and output a second differential signal;
- a third differential amplifier coupled to two switches, selectively coupled to the second signal pad and the third signal pad or the third signal pad and a fourth signal pad, arranged to receive signals on the second signal pad and the third signal pad or the third signal pad and the fourth signal pad and output a third differential signal;
- a fourth differential amplifier coupled to the fourth signal pad and a fifth signal pad, arranged to receive signals on the fourth signal pad and the fifth signal pad and output a fourth differential signal;
- a fifth differential amplifier coupled to the fourth signal pad and a sixth signal pad, arranged to receive signals on the fourth signal pad and the sixth signal pad and output a fifth differential signal;
- a sixth differential amplifier coupled to the fifth signal pad and the sixth signal pad, arranged to receive signals on the fifth signal pad and the sixth signal pad and output a sixth differential signal;
- a first signal processing block coupled to the first differential amplifier, arranged to process the first differential signal when the six-signal PMA is operated in a first PHY mode;
- a second signal processing block coupled to the first, second and third differential amplifiers, arranged to process the first, second and third differential signals when the six-signal PMA is operated in a second PHY mode;
- and
- a third signal processing block coupled to the third differential amplifier, arranged to process the third differential signal when the six-signal PMA is operated in the first PHY mode;
- a fourth signal processing block coupled to the fourth, fifth and sixth differential amplifiers, arranged to process the fourth, fifth and sixth differential signals when the six-signal PMA is operated in the second PHY mode;
- and
- a fifth signal processing block coupled to the sixth differential amplifier, arranged to process the sixth differential signal when the six-signal PMA is operated in the first PHY mode.
14 more elements
A clock and data recovery (CDR) circuit for a multi-wire interface, comprising:
- a plurality of XOR gates, each coupled to one wire of the multi-wire interface and each having a normal input and a delay input with a delay element, wherein each XOR gate receives a same signal on the wire from the normal input and the delay input and performs an XOR operation on the received signal and a delay version of the received signal, thereby to output an XOR output signal;
- a plurality of latches, each coupled to one of the XOR gates and arranged latch a predetermined signal according to one of XOR output signals to output a latch output signal, wherein the latches are resettable by a reset control signal;
- an OR gate coupled to latches, arranged to perform an OR operation on latch output signals to output a clock signal;
- and
- a duty cycle correction unit, coupled to the OR gate, arranged to generate the reset control signal to correct the clock signal according to the clock signal, so as to achieve 50% duty cycle for the clock signal.
2 more elements
A CDR circuit for a multi-wire interface, comprising:
- a plurality of XOR gates, each coupled to one wire of the multi-wire interface and each having a normal input and a delay input with a delay element, wherein each XOR gate receives a same signal on the wire from the normal input and the delay input and performs an XOR operation on the received signal and a delay version of the received signal, thereby to output an XOR output signal;
- a plurality of latches, each coupled to one of the XOR gates and arranged latch a predetermined signal according to one of XOR output signals to output a latch output signal, wherein the latches are resettable by a reset control signal;
- an OR gate coupled to latches, arranged to perform an OR operation on latch output signals to output a clock signal;
- and
- a delay adjustment unit, coupled to the OR gate, arranged to generate the reset control signal according to a plurality of output signals of a plurality of sampling unit.
2 more elements
Dependencies are inferred from the claim text.