# US 2018/0323806 A1 · Sliding window list decoder for error correcting codes

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- Number: US 2018/0323806 A1
- Document ID: US20180323806A1
- Status: Published application
- Kind: A1
- Application number: 16/036,206
- Filed: 2018-07-16
- Published: 2018-11-08
- Earliest claimed: 2014-09-22
- Assignees: Streamscale, Inc.
- Applicants: Streamscale, Inc.
- Inventors: Michael H. Anderson
- Web page: https://patentgrep.com/patent/US20180323806A1

## CPC

- H03M 13/1595: {Parallel or block-wise remainder calculation}
- H03M 13/091: {Parallel or block-wise CRC computation}
- H03M 13/1515: {Reed-Solomon codes}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/158: {Finite field arithmetic processing}
- H03M 13/6561: {Parallelized implementations}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

## Claims

### Claim 1

A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword, the system comprising:
an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors, the error-detecting circuit comprising:
a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword; and
a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.