# US 2018/0323796 A1 · Circuit and method for generating reference signals for hybrid analog-to-digital convertors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0323796 A1
- Document ID: US20180323796A1
- Status: Published application
- Kind: A1
- Application number: 16/031,753
- Filed: 2018-07-10
- Published: 2018-11-08
- Earliest claimed: 2016-09-08
- Assignees: STMicroelectronics International N.V.
- Applicants: STMicroelectronics International N.V.
- Inventors: Ashish KUMAR; Chandrajit Debnath; Pratap Narayan Singh
- Web page: https://patentgrep.com/patent/US20180323796A1

## CPC

- H03M 1/466: {using switched capacitors}
- H03M 1/0863: {of switching transients, e.g. glitches}
- H03M 1/1009: {Calibration}
- H03M 1/124: {Sampling or signal conditioning arrangements specially adapted for A/D converters}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)}
- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03M 1/44: Sequential comparisons in series-connected stages with change in value of analogue signal
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

## Claims

### Claim 1

A circuit configured to generate a plurality of reference signals for an analog-to-digital convertor (ADC) comprising a first stage and a second stage, the circuit comprising:
a first reference source comprising a first output terminal and a second output terminal coupled to respective terminals of the first stage of the ADC, the first reference source being configured to generate a first reference voltage between the first output terminal and the second output terminal of the first reference source, the first reference voltage being configured to be provided as a first reference signal to the first stage of the ADC, the first reference voltage comprising a first transient signal generated by the first stage of the ADC;
a filter coupled to the first output terminal and the second output terminal of the first reference source and configured to filter the first transient signal from the first reference signal to produce a filtered first reference signal; and
a second reference source having input terminals coupled to the filter, wherein the filter comprises at least one first capacitive element coupled between the input terminals of the second reference source, the second reference source comprising a first output terminal and a second output terminal coupled to respective terminals of the second stage of the ADC, the second reference source configured to generate a second reference signal between the first output terminal and the second output terminal of the second reference source based on the filtered first reference signal, the second reference signal being configured to be provided as a second reference signal to the second stage of the ADC.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising at least one second capacitive element coupled to at least one of the first output terminal or the second output terminal of the second reference source, the at least one second capacitive element being configured to shunt a second transient signal generated by the second stage of the ADC.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the at least one second capacitive element is coupled between the first output terminal and the second output terminal of the second reference source.

### Claim 4 (depends on 2)

The circuit of claim 2, wherein the at least one second capacitive element is coupled between the first output terminal of the second reference source and a supply voltage.

### Claim 5 (depends on 2)

The circuit of claim 2, wherein the at least one second capacitive element is configured to mitigate an effect of the second transient signal on at least one of the first reference signal or the filtered first reference signal.

### Claim 6 (depends on 2)

The circuit of claim 2, wherein the second transient signal is generated in response to capacitor switching in the second stage of the ADC.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein an architecture of the first stage of the ADC is different from an architecture of the second stage of the ADC.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the first transient signal is generated in response to capacitor switching in the first stage of the ADC.

### Claim 9 (depends on 1)

The circuit of claim 1, wherein the first stage of the ADC is configured to receive an analog signal, wherein the first stage of the ADC is configured to determine M most significant bits of an N-bit digital representation of the analog signal, and wherein the second stage of the ADC is configured to determine (N-M) least significant bits of the N-bit digital representation of the analog signal.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the first stage of the ADC is configured to determine the M most significant bits of the N-bit digital representation of the analog signal based on the first reference signal.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein the second stage of the ADC is configured to determine the (N-M) least significant bits of the N-bit digital representation of the analog signal based on the second reference signal.

### Claim 12

A circuit configured to generate a plurality of reference signals for an analog-to-digital convertor (ADC) comprising a first stage and a second stage, the first stage and the second stage having differing ADC architectures, the circuit comprising:
a low pass filter comprising an input terminal, an output terminal, and at least one first capacitive element;
a first reference source having an output coupled to the input terminal of the low pass filter and to the first stage of the ADC, the first reference source being configured to provide a first reference signal to the first stage of the ADC, the low pass filter being configured to filter a first transient signal, generated by the first stage of the ADC, from the first reference signal, the low pass filter being configured to generate a filtered first reference signal based on the first reference signal; and
a second reference source having an input coupled to the output terminal of the low pass filter, wherein the at least one first capacitive element of the low pass filter is coupled across the input of the second reference source, the second reference source further having an output coupled to the second stage of the ADC, the second reference source being configured to provide a second reference signal to the second stage of the ADC, the second reference source being configured to generate the second reference signal based on the filtered first reference signal.

### Claim 13 (depends on 12)

The circuit of claim 12, further comprising a second capacitive element coupled to the output of the second reference source, the second capacitive element being configured to shunt a second transient signal, generated by the second stage of the ADC, to mitigate an effect of the second transient signal on at least one of the first reference signal or the filtered first reference signal.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein the first stage of the ADC is configured to receive an analog signal, wherein the first stage of the ADC is configured to determine M most significant bits of an N-bit digital representation of the analog signal, and wherein the second stage of the ADC is configured to determine (N-M) least significant bits of the N-bit digital representation of the analog signal.

### Claim 15 (depends on 14)

The circuit of claim 14, wherein a capacitance of the second capacitive element is 2 N-M times greater than a total digital-to-analog capacitance of the second stage of the ADC.

### Claim 16 (depends on 12)

The circuit of claim 12, wherein a frequency of the first transient signal is proportional to a frequency of capacitor-switching in the first stage of the ADC, and wherein a cutoff frequency of the low pass filter is between about 5 times to about 10 times less than a frequency of the first transient signal.

### Claim 17 (depends on 12)

The circuit of claim 12, wherein the first stage of the ADC comprises a pipeline ADC.

### Claim 18 (depends on 12)

The circuit of claim 12, wherein the second stage of the ADC comprises at least one of a successive-approximation register (SAR) ADC, an asynchronous SAR ADC, a time-interleaved SAR ADC, or a time-interleaved asynchronous SAR ADC.

### Claim 19 (depends on 12)

The circuit of claim 12, wherein at least one of the first reference source or the second reference source comprises a first pair of single-ended voltage followers connected in parallel.

### Claim 20 (depends on 12)

The circuit of claim 12, wherein at least one of the first reference source or the second reference source comprises a fully differential amplifier.