# US 2018/0323794 A1 · Method for synchronising data converters by means of a signal transmitted from one to the next

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- Number: US 2018/0323794 A1
- Document ID: US20180323794A1
- Status: Published application
- Kind: A1
- Application number: 15/774,455
- Filed: 2016-11-04
- Published: 2018-11-08
- Earliest claimed: 2015-11-10
- Assignees: Teledyne E2V Semiconductors SAS
- Applicants: Teledyne e2v Semiconductors SAS
- Inventors: Etienne BOUIN; Rémi LAUBE; Jérôme LIGOZAT; Marc STACKLER
- Web page: https://patentgrep.com/patent/US20180323794A1

## CPC

- H03M 1/0624: {by synchronisation}
- H03K 5/1534: Transition or edge detectors
- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H03K 2005/00267: {using D/A or A/D converters}
- H03M 1/1215: {using time-division multiplexing}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

## Claims

### Claim 1

A method for synchronizing digital/analogue and/or analogue/digital data converters to an active front of a common reference clock CLK, characterized in that the converters form at least one series transmission chain allowing a synchronizing signal emitted by a unit for controlling the converters to be transmitted, method such that:
the converter of rank 1 in the chain has a synchronization input connected to a synchronization control output of the control unit;
each converter of rank j higher than 1 in the chain has a synchronization input connected to the synchronization output of the converter of rank j−1 in the chain;
the synchronizing method being characterized in that a procedure for synchronizing the converters of the chain to a reference-clock active front activated by the control unit comprises the following steps, which are controlled by the control unit:
a step of initializing, in each converter, a synchronization configuration register including at least one polarity parameter defining the polarity of a reference-clock front for detection of signals input via the synchronization input of the converter as the polarity of the reference-clock active front or the inverse polarity; then
sending to the synchronization control output of the control unit a synchronizing signal, which is a pulse of width at least equal to one reference-clock period; and
the synchronizing method also being characterized in that each converter in the chain is configured to carry out the following steps:
a) a step of detecting, on a CLK reference-clock front, that front has the polarity defined by the value of said polarity parameter configured in the converter, a synchronizing signal input via the synchronization input, and
b) a step of aligning with the following reference-clock active front the signal detected in step a), so as to deliver a synchronizing signal aligned with a reference-clock active front, and applying said signal to the synchronization output of the converter.

### Claim 2 (depends on 1)

The method of claim 1, wherein each converter in the chain is formed from n cores converting at a sampling frequency that is delivered by a divider by n of the reference-clock frequency, where n is a nonzero integer, and configured to carry out, following step b), the following steps:
c) a step of shifting said aligned synchronizing signal obtained in step b) by an integer number of reference-clock period(s), which integer number is defined by the value of a phase parameter delivered by said configuration register of the converter; and
d) a step of using the obtained shifted signal as a signal for resetting said divider of frequency by n,
said integer number defined by the phase parameter having a value comprised between 0 and n−1, inclusive of limits.

### Claim 3 (depends on 1)

The method of claim 1, wherein each converter in the chain is furthermore configured to carry out the following step:
e) a step of verifying the stability of an active level of the signal received via the synchronization input and acquired on the reference-clock front defined in the detecting step a) by the value of said polarity parameter, by comparing the first value acquired on said detecting front to at least one second value of said signal, which value is acquired on a front that is ahead, by a set time, of said detecting front and to at least one third value of said signal, which value is acquired on a front that is behind, by a set time, said detecting front, and if the values are not all identical, activating a corresponding flag bit in said configuration register of the converter.

### Claim 4 (depends on 3)

The method of claim 3, wherein the flag bit of the configuration register of the converters is used by the control unit in a setting phase to change the value of the polarity parameter in each converter of a chain, from a first binary value initialized by default to a second binary value, and in that, in said setting phase, the control unit emits a new synchronizing signal each time a flag bit is activated in the configuration register of a converter of the chain, said setting phase allowing the polarity parameter of each converter, in succession from the first converter at the input of the chain to the last converter of the chain, to be configured.

### Claim 5 (depends on 4)

The method of claim 4, wherein after said step of setting the polarity parameters of the converters, a value p of the phase parameter of each converter is determined on the basis of a determination of the integer number M of reference-clock periods separating the synchronizing pulse front output from the converter via its output from the synchronizing pulse front output from an upstream converter in the chain, and the value p of the phase parameter is such that the sum M+p is a multiple of n.

### Claim 6 (depends on 1)

The method of claim 1, wherein the synchronizing signal emitted by the control unit is a signal synchronized to an active front of the reference clock CLK.

### Claim 7 (depends on 1)

The method of claim 1, wherein the procedure for synchronizing the converters of the chain comprises the emission, by the control unit, of an asynchronous synchronizing signal and in that the control unit emits a new asynchronous synchronizing signal each time the flag bit is activated in the configuration register of the converter of rank 1 at the input of the chain.

### Claim 8

An analogue/digital or digital/analogue data converter comprising an input for receiving a synchronizing signal and an associated synchronizing circuit allowing the converter to be synchronized to an active front of a reference-clock signal, the converter comprising a configuration register that may be read from and written to via an interface bus by a control unit of the converter, said register comprising at least one polarity parameter defining a reference-clock-front polarity for detection of said synchronizing signal received as input, and the synchronizing circuit comprising a detecting circuit that comprises:
a) a stage for detecting, on a reference-clock front that has the polarity defined by the binary value of said polarity parameter, an active level of said received synchronizing signal, and
b) a stage for aligning the synchronizing signal detected by the detecting stage, which delivers as output a synchronizing signal aligned with a reference-clock active front, and said aligned synchronizing signal is applied to a synchronization output of the converter.

### Claim 9 (depends on 8)

The converter of claim 8, which is formed from n cores converting at a sampling frequency that is delivered by a divider by n of the reference-clock frequency, where n is a nonzero integer, characterized in that the configuration register contains another phase parameter the value of which is equal to an integer number comprised between 0 and n−1, inclusive of limits, and in that the synchronizing circuit comprises a shifting circuit configured to apply to the signal delivered as output from said aligning stage, a shift of an integer number of reference-clock periods, which is given by the value of said phase parameter, and to use the obtained shifted signal as a signal for resetting the divider of frequency by n.

### Claim 10 (depends on 8)

The converter of claim 8, wherein the synchronizing circuit comprises a circuit for verifying the stability of an active level of the synchronizing signal received via the input, which comprises a first stage for acquiring a level of said synchronizing signal on a reference-clock front having the polarity defined by the value of said polarity parameter, at least one second stage for acquiring a level of said synchronizing signal on a front that is ahead, by a set time, of said reference-clock front defined in the first stage, and at least one third stage for acquiring a level of said synchronizing signal on a front that is behind, by a set time, said reference-clock front defined in the first stage, and if the values delivered by the various stages are not all identical, the output of said verifying circuit activates a flag bit in said configuration register of the converter.

### Claim 11 (depends on 2)

The method of claim 2, wherein each converter in the chain is furthermore configured to carry out the following step:
e) a step of verifying the stability of an active level of the signal received via the synchronization input and acquired on the reference-clock front defined in the detecting step a) by the value of said polarity parameter, by comparing the first value acquired on said detecting front to at least one second value of said signal, which value is acquired on a front that is ahead, by a set time, of said detecting front and to at least one third value of said signal, which value is acquired on a front that is behind, by a set time, said detecting front, and if the values are not all identical, activating a corresponding flag bit in said configuration register of the converter.

### Claim 12 (depends on 2)

The method of claim 2, wherein the synchronizing signal emitted by the control unit is a signal synchronized to an active front of the reference clock CLK.

### Claim 13 (depends on 3)

The method of claim 3, wherein the synchronizing signal emitted by the control unit is a signal synchronized to an active front of the reference clock CLK.

### Claim 14 (depends on 4)

The method of claim 4 wherein the synchronizing signal emitted by the control unit is a signal synchronized to an active front of the reference clock CLK.

### Claim 15 (depends on 5)

The method of claim 5, wherein the synchronizing signal emitted by the control unit is a signal synchronized to an active front of the reference clock CLK.

### Claim 16 (depends on 2)

The method of claim 2, wherein the procedure for synchronizing the converters of the chain comprises the emission, by the control unit, of an asynchronous synchronizing signal and in that the control unit emits a new asynchronous synchronizing signal each time the flag bit is activated in the configuration register of the converter of rank 1 at the input of the chain.

### Claim 17 (depends on 3)

The method of claim 3, wherein the procedure for synchronizing the converters of the chain comprises the emission, by the control unit, of an asynchronous synchronizing signal and in that the control unit emits a new asynchronous synchronizing signal each time the flag bit is activated in the configuration register of the converter of rank 1 at the input of the chain.

### Claim 18 (depends on 4)

The method of claim 4, wherein the procedure for synchronizing the converters of the chain comprises the emission, by the control unit, of an asynchronous synchronizing signal and in that the control unit emits a new asynchronous synchronizing signal each time the flag bit is activated in the configuration register of the converter of rank 1 at the input of the chain.

### Claim 19 (depends on 5)

The method of claim 5, wherein the procedure for synchronizing the converters of the chain comprises the emission, by the control unit, of an asynchronous synchronizing signal and in that the control unit emits a new asynchronous synchronizing signal each time the flag bit is activated in the configuration register of the converter of rank 1 at the input of the chain.

### Claim 20 (depends on 6)

The method of claim 6, wherein the procedure for synchronizing the converters of the chain comprises the emission, by the control unit, of an asynchronous synchronizing signal and in that the control unit emits a new asynchronous synchronizing signal each time the flag bit is activated in the configuration register of the converter of rank 1 at the input of the chain.