# US 2018/0323786 A1 · Dynamic decode circuit with active glitch control method

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- Number: US 2018/0323786 A1
- Document ID: US20180323786A1
- Status: Published application
- Kind: A1
- Application number: 16/029,604
- Filed: 2018-07-08
- Published: 2018-11-08
- Earliest claimed: 2016-09-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Paul Alan Bunce; Yuen Hung Chan; John D. Davis; Antonio Raffaele Pelella
- Web page: https://patentgrep.com/patent/US20180323786A1

## CPC

- H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)}
- G11C 8/10: Decoders
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

## Claims

### Claim 1

A method for precharging a dynamic decode circuit, the dynamic decode circuit comprising a decoder connected to a first node and an evaluate circuit, the evaluate circuit comprising a first transistor serially connected to a second transistor by way of an interconnecting node, the evaluate circuit connected between a second node and a first power source, the dynamic decode circuit performing a method, the method comprising:
receiving input signals, by a plurality of inputs of the decoder;
based on the plurality of inputs of the decoder being in a predetermined input state and based on being in an evaluation phase, causing, by the decoder, the first node to be low;
receiving an evaluation clock signal by a first gate of the first transistor of the evaluate circuit;
receiving the first node by a second gate of the second transistor of the evaluate circuit;
based on the first node being low and based on being in the evaluation phase, causing, by the evaluate circuit, the second node to be high;
precharging the first node to a high state, by a first precharge circuit comprising a first precharge transistor, based on not being in the evaluation phase of the evaluation clock signal;
precharging the second node to the high state, by a second precharge circuit comprising a second precharge transistor, based on not being in the evaluation phase of the evaluation clock signal; and
precharging the interconnecting node of the evaluate circuit to the high state, by a third precharge circuit comprising a third precharge transistor, based on not being in the evaluation phase of the evaluation clock signal.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the decoder is further connected to a third node, further comprising based on being in the evaluation phase, causing, by the first transistor of the evaluate circuit, the second node to be low;

### Claim 3 (depends on 1)

The method according to claim 1, wherein at least one of the precharge circuits consists of two serially connected precharge transistors, further comprising delaying start of the precharging to the high state based on a delay precharge gate of a delay precharge transistor of the precharge circuit receiving a delayed evaluation clock signal.

### Claim 4 (depends on 4)

The method according to claim 4, further comprising creating the delayed evaluation clock signal from the evaluation clock signal.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the dynamic decode circuit is configured to be one of a plurality of dynamic decode circuits having a shared node, each dynamic decode circuit having a conditioning transistor, each conditioning transistor of the plurality of dynamic decode circuits connected in parallel to the shared node, the method further comprising:
causing, by the each of the plurality of dynamic circuits, the shared node to be in a conditioned state, by a conditioning transistor, wherein the conditioning transistor consists of any one of a precharge transistor and an evaluate transistor.

### Claim 6 (depends on 5)

The method according to claim 5, wherein only a predetermined maximum number of decoders of the plurality of dynamic decode circuits can cause a respective first node to be low, wherein size of the conditioning transistor is determined by a ratio of the predetermined maximum number to a total number of dynamic decode circuits.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the predetermined maximum number is 1.

### Claim 8 (depends on 1)

The method according to claim 1, wherein each respective precharge circuit is configured to precharge a respective node based on the evaluation clock signal being low, and wherein the precharge circuit is configured to not conduct based on the evaluation clock signal being high.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the dynamic decode circuit is configured to be 1 of N dynamic decode circuits having a shared node shared by the N dynamic decode circuits, each dynamic decode circuit having a conditioning transistor, each respective conditioning transistor of the plurality of dynamic decode circuits connected in parallel to the shared node, the method further comprising:
providing, by the conditioning transistor of the each dynamic decode circuit of the plurality of dynamic decode circuits, 1/N of the current to the shared node needed to precharge the shared node, wherein the conditioning transistor size is based on having only to supply the 1/N of the current.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the dynamic decode circuit is configured to be 1 of N dynamic decode circuits having a shared node shared by the N dynamic decode circuits, each dynamic decode circuit having a conditioning transistor, each conditioning transistor of the plurality of dynamic decode circuits connected in parallel to the shared node, the method further comprising:
providing, by the conditioning transistor of the each dynamic decode circuit of the plurality of dynamic decode circuits, 1/N of the current to the shared node needed to evaluate the shared node in the evaluation phase, wherein the conditioning transistor size is based on having only to supply the 1/N of the current.

### Claim 11 (depends on 1)

The method according to claim 1, further comprising:
based the plurality of inputs of the decoder not being in the predetermined input state and based on being in the evaluation phase, causing, by the decoder, the first node to be high; and
based on the first node being high and based on being in the evaluation phase, causing, by the evaluate circuit, the second node to be low;

### Claim 12 (depends on 1)

The method according to claim 1, wherein the predetermined input state of the plurality of inputs is all inputs being high.

### Claim 13 (depends on 1)

The method according to claim 1, wherein the predetermined input state of the plurality of inputs is all inputs being low.