# US 2018/0323757 A1 · High power rf switches using multiple optimized transistors

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- Number: US 2018/0323757 A1
- Document ID: US20180323757A1
- Status: Published application
- Kind: A1
- Application number: 16/025,996
- Filed: 2018-07-02
- Published: 2018-11-08
- Earliest claimed: 2015-06-09
- Assignees: Newport Fab, LLC dba Jazz Semiconductor
- Applicants: Newport Fab, LLC dba Jazz Semiconductor, Inc.
- Inventors: Paul D. Hurwitz; Roda Kanawati
- Web page: https://patentgrep.com/patent/US20180323757A1

## CPC

- H03F 3/245: {with semiconductor devices only}
- H03K 17/102: {in field-effect transistor switches}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H03F 2200/421: Multiple switches coupled in the output circuit of an amplifier are controlled by a circuit
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.

## Claims

### Claim 1

A switch comprising:
a plurality of field effect transistors connected in series between a first node and a second node, wherein the plurality of field effect transistors include:
a first transistor having a first body region having a first conductivity type, a first set of lightly doped drain (LDD) regions having a second conductivity type, opposite the first conductivity type, and a first set of halo implant regions of the second conductivity type located between the first set of LDD regions and the first body region, and
a second transistor having a second body region having the first conductivity type, and a second set of LDD regions having the second conductivity type, wherein the second transistor does not include halo implant regions located between the second set of LDD regions and the second body region, and wherein the first transistor has a higher breakdown voltage than the second transistor.

### Claim 2 (depends on 1)

The switch of claim 1, wherein the first set of LDD regions has a dopant concentration lower than a dopant concentration of the second set of LDD regions.

### Claim 3 (depends on 2)

The switch of claim 2, wherein the first set of LDD regions extend a first depth into the first body region, and the second set of LDD regions extend a second depth into the second body region, wherein the first depth is greater than the second depth.

### Claim 4 (depends on 1)

The switch of claim 1, wherein the first body region has a dopant concentration equal to a dopant concentration of the second body region.

### Claim 5 (depends on 1)

The switch of claim 1, wherein the first and second body regions are located on a buried oxide layer.

### Claim 6 (depends on 1)

The switch of claim 1, wherein the first node comprises a power amplifier output and the second node comprises an antenna input.

### Claim 7 (depends on 1)

The switch of claim 1, wherein the first transistor has a first channel length and the second transistor has a second channel length, wherein the first channel length is the same as the second channel length.

### Claim 8

A method of fabricating a switch including a first transistor and a second transistor coupled in series between a first node and a second node, the method comprising:
forming the first transistor in a first body region having a first conductivity type, wherein the first transistor includes a first set of lightly doped drain (LDD) regions having a second conductivity type,
forming the second transistor in a second body region having the first conductivity type, wherein the second transistor includes a second set of LDD regions having the second conductivity type; and
performing halo implants having the first conductivity type to the first transistor, but not the second transistor, wherein the halo implants result in the formation of a set of halo regions between the first set of LDD regions and the first body regions.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
performing a first implant to form the first set of lightly doped drain (LDD) regions; and
performing a second implant to form a second set of LDD regions, wherein the first implant has a lower dosage than the second implant.

### Claim 10 (depends on 9)

The method of claim 9, further comprising performing the first implant at a higher implant energy than the second implant.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first body region has a dopant concentration equal to a dopant concentration of the second body region.

### Claim 12 (depends on 8)

The method of claim 8, wherein the first transistor has a first channel length and the second transistor has a second channel length, wherein the first channel length is the same as the second channel length.