# US 2018/0323347 A1 · Thin film transistor, display substrate, methods for manufacturing the same and display device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0323347 A1
- Document ID: US20180323347A1
- Status: Published application
- Kind: A1
- Application number: 15/871,525
- Filed: 2018-01-15
- Published: 2018-11-08
- Earliest claimed: 2017-05-08
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Wei Liu
- Web page: https://patentgrep.com/patent/US20180323347A1

## CPC

- H10H 20/84: Coatings, e.g. passivation layers or antireflective coatings
- H10D 30/6723: {having light shields}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10H 20/01: Manufacture or treatment
- H10H 20/83: Electrodes
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10K 59/126: Shielding, e.g. light-blocking means over the TFTs
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A thin film transistor, a display substrate, manufacturing methods thereof, and a display device are provided. The manufacturing method for the thin film transistor includes: forming a light-shielding metal pattern and a source-drain metal layer pattern on a base substrate; forming a buffer layer including first and second via-holes; forming a source electrode connected with the light-shielding metal pattern via the first via-hole, a drain electrode connected with the source-drain metal layer pattern via the second via-hole, and an active layer, an orthographic projection of the light-shielding metal pattern on the substrate completely covering that of the active layer on the substrate and at least partially covering those of the source and drain electrodes on the substrate; and forming a gate insulation layer and a gate electrode, orthographic projections of the gate insulation layer and the gate electrode on the substrate being identical.

## Claims

### Claim 1

A method for manufacturing a thin film transistor, comprising:
forming a light-shielding metal pattern and a source-drain metal layer pattern on a base substrate;
forming a buffer layer covering the light-shielding metal pattern and the source-drain metal layer pattern, and patterning the buffer layer to form a first via-hole exposing a part of the light-shielding metal pattern and a second via-hole exposing a part of the source-drain metal layer pattern;
forming a semiconductor layer pattern on the buffer layer, wherein the semiconductor layer pattern comprises a source electrode region, a drain electrode region, and an active layer between the source electrode region and the drain electrode region, an orthographic projection of the light-shielding metal pattern on the base substrate completely covers an orthographic projection of the active layer on the base substrate and at least covers a part of an orthographic projection of the source electrode region on the base substrate and a part of an orthographic projection of the drain electrode region on the base substrate, the source electrode region is electrically connected with the light-shielding metal pattern via the first via-hole, and the drain electrode region is electrically connected with the source-drain metal layer pattern via the second via-hole; and
forming a gate insulation layer pattern and a gate electrode on the semiconductor layer pattern, wherein an orthographic projection of the gate insulation layer pattern on the base substrate coincides with an orthographic projection of the gate electrode on the base substrate.

### Claim 2 (depends on 1)

The method for manufacturing a thin film transistor according to claim 1, further comprising:
performing conductive treatment on the source electrode region and the drain electrode region by implanting metal ions or performing plasma treatment and by taking the gate electrode as a mask, so as to form a source electrode and a drain electrode of the thin film transistor, respectively.

### Claim 3 (depends on 1)

The method for manufacturing a thin film transistor according to claim 1, wherein forming the light-shielding metal pattern and the source-drain metal layer pattern on the base substrate comprises:
forming the light-shielding metal pattern and the source-drain metal layer pattern on the base substrate simultaneously in a first patterning process, and wherein forming the gate insulation layer pattern and the gate electrode comprises:
forming the gate insulation layer pattern and the gate electrode simultaneously in a second patterning process.

### Claim 4 (depends on 1)

The method for manufacturing a thin film transistor according to claim 1, wherein forming the semiconductor layer pattern on the buffer layer comprises forming the semiconductor layer pattern on the buffer layer by using a metal oxide semiconductor material.

### Claim 5 (depends on 1)

The method for manufacturing a thin film transistor according to claim 1, wherein forming the light-shielding metal pattern and the source-drain metal layer pattern on the base substrate comprises:
depositing a metal layer on the base substrate by using a sputtering process or a thermal-evaporation process; and
patterning the metal layer to simultaneously form the light-shielding metal pattern and the source-drain metal layer pattern,
wherein the base substrate is a glass substrate or a quartz substrate, and the metal layer is formed of any one of Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or any combination of Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, and W.

### Claim 6

A thin film transistor, comprising:
a light-shielding metal pattern and a source-drain metal layer pattern on a base substrate and in an identical layer;
a buffer layer covering the light-shielding metal pattern and the source-drain metal layer pattern, wherein the buffer layer comprises a first via-hole corresponding to the light-shielding metal pattern and a second via-hole corresponding to the source-drain metal layer pattern;
a source electrode, a drain electrode and an active layer on the buffer layer, wherein an orthographic projection of the light-shielding metal pattern on the base substrate completely covers an orthographic projection of the active layer on the base substrate and at least covers a part of an orthographic projection of the source electrode on the base substrate and a part of an orthographic projection of the drain electrode on the base substrate, and the source electrode is electrically connected with the light-shielding metal pattern via the first via-hole, and the drain electrode is electrically connected with the source-drain metal layer pattern via the second via-hole;
a gate insulation layer pattern on the active layer; and
a gate electrode on the gate insulation layer pattern, wherein an orthographic projection of the gate electrode on the base substrate coincides with an orthographic projection of the gate insulation layer pattern on the base substrate.

### Claim 7 (depends on 6)

The thin film transistor according to claim 6, wherein an orthographic projection of the active layer on the base substrate coincides with the orthographic projection of the gate insulation layer pattern on the base substrate, and contents of metal ions in the source electrode and the drain electrode are higher than contents of metal ions in the active layer.

### Claim 8 (depends on 1)

A method for manufacturing a display substrate, comprising:
manufacturing a thin film transistor on a base substrate by using the method according to claim 1.

### Claim 9 (depends on 8)

The method for manufacturing a display substrate according to claim 8, wherein after manufacturing the thin film transistor, the method further comprises:
forming a passivation layer covering the gate electrode, the source electrode region, the drain electrode region and the buffer layer, and patterning the passivation layer to form a third via-hole exposing a part of the drain electrode region of the thin film transistor; and
forming a pattern of a pixel electrode on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode region via the third via-hole.

### Claim 10 (depends on 8)

The method for manufacturing a display substrate according to claim 8, further comprising:
performing conductive treatment on the source electrode region and the drain electrode region by implanting metal ions or performing plasma treatment and by taking the gate electrode as a mask, so as to form a source electrode and a drain electrode of the thin film transistor, respectively.

### Claim 11 (depends on 6)

A display substrate, comprising:
the thin film transistor on the base substrate according to claim 6.

### Claim 12 (depends on 11)

The display substrate according to claim 11, wherein an orthographic projection of the active layer on the base substrate coincides with an orthographic projection of the gate insulation layer pattern on the base substrate, and contents of metal ions in the source electrode and the drain electrode are higher than contents of metal ions in the active layer.

### Claim 13 (depends on 11)

The display substrate according to claim 11, further comprising:
a passivation layer covering the thin film transistor; and
a pixel electrode electrically connected with the drain electrode of the thin film transistor via a third via-hole penetrating through the passivation layer.

### Claim 14 (depends on 11)

A display device, comprising:
a display substrate according to claim 11.