# US 2018/0323341 A1 · Semiconductor device

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- Number: US 2018/0323341 A1
- Document ID: US20180323341A1
- Status: Published application
- Kind: A1
- Application number: 15/772,907
- Filed: 2016-11-03
- Published: 2018-11-08
- Earliest claimed: 2015-11-03
- Assignees: LG Innotek Co., Ltd.
- Applicants: LG Innotek Co., Ltd.
- Inventors: Ji Hyun KOO; Dae Hee LEE; Jung Wook LEE
- Web page: https://patentgrep.com/patent/US20180323341A1

## CPC

- H10H 20/8162: {Current-blocking structures}
- H10H 20/81: Bodies
- H10H 20/816: having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
- H10H 20/82: Roughened surfaces, e.g. at the interface between epitaxial layers
- H10H 20/83: Electrodes
- H10H 20/831: characterised by their shape
- H10H 20/8312: {extending at least partially through the bodies}
- H10H 20/835: {Reflective materials}
- H10H 20/85: Packages
- H10H 20/84: Coatings, e.g. passivation layers or antireflective coatings
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A semiconductor device according to an embodiment includes: a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a plurality of recesses exposing a lower portion of the first conductive semiconductor layer; at least one pad arranged outside the light emitting structure and arranged to be adjacent to at least one edge; and a plurality of insulation patterns arranged in the recesses and extending to a lower surface of the light emitting structure, in which widths of the plurality of insulation patterns are reduced as the insulation patterns become further away from the pad. The semiconductor device according to the embodiment may prevent a current from being focused on a recess area adjacent to the pad.

## Claims

### Claim at position 1

1-10. (canceled)

### Claim 11

A semiconductor device comprising:
a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a plurality of recesses through which a lower portion of the first conductive semiconductor layer is exposed;
at least one pad arranged outside the light emitting structure, and arranged to be adjacent to at least one edge; and
a plurality of insulation patterns arranged inside the recesses and extending to a lower surface of the light emitting structure,
wherein widths of the plurality of insulation patterns are reduced as the insulation patterns become further away from the pad.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the plurality of insulation patterns include first to sixth insulation patterns, and
wherein the first to sixth insulation patterns are arranged from a first edge adjacent to the pad toward a second edge diagonally facing the first edge.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein when a width of the first insulation pattern is 100%, a width of the sixth insulation pattern is 65% or more.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein when a width of the first insulation pattern is 100%, a width of the second insulation pattern is 93% to 95%, a width of the third insulation pattern is 86% to 90%, a width of the fourth insulation pattern is 79% to 85%, a width of the fifth insulation pattern is 72% to 80%, and a width of the sixth insulation pattern is 65% to 75%.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the plurality of recesses are arranged on the light emitting structure at regular intervals, and the plurality of recesses have a constant width, and
wherein the semiconductor device further comprises second electrodes arranged inside the plurality of recesses and being directly in contact with the first conductive semiconductor layer exposed from the recesses.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the plurality of insulation patterns surround the second electrodes, and intervals between the plurality of adjacent insulation patterns become larger as the insulation patterns become further away from the pad.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein the plurality of insulation patterns include first to sixth insulation patterns, and
wherein when a first interval between the first insulation pattern adjacent to the pad and the second insulation pattern is 100%, a second interval between the second and third insulation patterns is 94% to 97%, a third interval between the third and fourth insulation patterns is 91% to 94%, a fourth interval between the fourth and fifth insulation patterns is 88% to 91%, a fifth interval between the fifth and sixth insulation patterns is 85% to 88%.

### Claim 18 (depends on 11)

The semiconductor device of claim 11, wherein the pad includes a first pad arranged to be adjacent to the first edge and a second pad arranged to be adjacent to the second edge, and
wherein widths of the plurality of insulation patterns are reduced as the insulation patterns go from the first edge toward a third edge in a diagonal direction.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the widths of the plurality of insulation patterns are reduced as the insulation patterns go from the second edge toward a fourth edge in a diagonal direction.

### Claim 20

A semiconductor device comprising:
a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, and a plurality of recesses extending from the second conductive semiconductor layer via the active layer to a part of the first conductive semiconductor layer;
first electrodes arranged inside the plurality of recesses and electrically connected to the first conductive semiconductor layer;
second electrodes electrically connected to the second conductive semiconductor layer; and
a pad portion including a first pad and a second pad electrically connected to the second electrodes,
wherein a first group of recesses among the plurality of recesses are spaced apart from each other between the first pad and the second pad by a first interval in a first direction connecting the first pad and the second pad,
wherein a second group of recesses among the plurality of recesses are arranged in the first direction to be spaced apart from each other by a second interval that is larger than the first interval in a second direction that is perpendicular to the first direction in the first group of recesses, and
wherein a third group of recesses among the plurality of recesses are arranged in the first direction to be spaced apart from each other by a third interval that is smaller than the first interval in the second direction in the second group of recesses.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein the third group of recesses include a 3-1 group of recesses adjacent to the second group of recesses to a 3-n group of recesses furthest away from the second group of recesses, and intervals between the second group of recesses to the 3-n group of recesses are increased at regular intervals as the recesses become closer to the pad portion.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein an interval between the 3-n group of recesses and the 3-(n−1) group of recesses is determined by an equation,
Ln=βL1,
wherein β is an arbitrary experimental value, and L1 is the first interval.

### Claim 23 (depends on 21)

The semiconductor device of claim 21, wherein an interval between the 3-n group of recesses and the 3-(n−1) group of recesses is ⅕ to 1/7 of the first interval.

### Claim 24 (depends on 20)

The semiconductor device of claim 20, wherein the second interval is 1.25 times to 1.35 times of the first interval.

### Claim 25 (depends on 20)

The semiconductor device of claim 20, wherein the second interval is determined by an equation,
L2=αL×βL1(α=1.4˜1.5,β=⅕˜ 1/7),
wherein L is the first interval.

### Claim 26 (depends on 21)

The semiconductor device of claim 21, wherein the semiconductor device further comprises current blocking layers surrounding the plurality of recesses, and thicknesses of the current blocking layers become larger as the current blocking layers become closer to the pad portion.

### Claim 27 (depends on 26)

The semiconductor device of claim 26, wherein a thickness of the current blocking layer arranged to be furthest away from the pad portion is 1/9 to 1/11 of the first interval.

### Claim 28

A semiconductor device comprising:
a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, and a plurality of recesses extending from the second conductive semiconductor layer via the active layer to a part of the first conductive semiconductor layer;
first electrodes arranged inside the plurality of recesses and electrically connected to the first conductive semiconductor layer;
second electrodes electrically connected to the second conductive semiconductor layer; and
a pad electrically connected to the second electrodes,
wherein a first group of recesses among the plurality of recesses are arranged to be adjacent to the pad in a first direction and a second direction that is perpendicular to the first direction at a first interval, and
wherein a second group of recesses among the plurality of recesses are arranged in a third direction between the first direction and the second direction at an interval that is smaller than the first interval in the first group of recesses.

### Claim 29 (depends on 28)

The semiconductor device of claim 28, wherein the second group of recesses include a 2-1 group of recesses adjacent to the first group of recesses to a 2-n group of recesses furthest away from the first group of recesses, and intervals between the second group of recesses are increased at regular intervals as the second group of recesses become closer to the pad.

### Claim 30 (depends on 29)

The semiconductor device of claim 29, wherein an interval between the 2-n group of recesses and the 2-(n−1) group of recesses is ⅕ to 1/7 of the first interval.