# US 2018/0323301 A1 · Method of making a cmos semiconductor device using a stressed silicon-on-insulator (soi) wafer

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- Number: US 2018/0323301 A1
- Document ID: US20180323301A1
- Status: Published application
- Kind: A1
- Application number: 16/035,458
- Filed: 2018-07-13
- Published: 2018-11-08
- Earliest claimed: 2013-10-08
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics, Inc.
- Inventors: Qing Liu; Nicolas Loubet
- Web page: https://patentgrep.com/patent/US20180323301A1

## CPC

- H10D 30/798: {being provided in or under the channel regions}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/171: {being group IV material}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

## Claims

### Claim 1

(canceled)

### Claim 2

A device, comprising:
a substrate;
an insulating layer on the substrate; and
a semiconductor layer on the insulating layer, the semiconductor layer having:
a first stressed portion of a first semiconductor material; and
a second stressed portion laterally adjacent to the first stressed portion, the second stressed portion including a first layer of the first semiconductor material on the insulating layer and a second layer of a second semiconductor material on the first layer;
a first trench isolation region extending through the insulating layer and into the substrate, the first trench isolation region separating the first and second stressed portions; and
a second trench isolation region extending through the insulating layer and into the substrate, the second stressed portion extending between the first trench isolation region and the second trench isolation region.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first layer of the second stressed portion is thinner than the first stressed portion.

### Claim 4 (depends on 2)

The device of claim 2, wherein the first layer of the second stressed portion is thinner than the second layer of the second stressed portion.

### Claim 5 (depends on 2)

The device of claim 2, wherein a surface of the first stressed portion is coplanar with a surface of the second stressed portion.

### Claim 6 (depends on 2)

The device of claim 2, further comprising a third trench isolation region extending through the insulating layer and into the substrate, the first stressed portion extending between the first trench isolation region and the third trench isolation region.

### Claim 7 (depends on 2)

The device of claim 2, further comprising:
a first gate stack on the first stressed portion; and
a second gate stack on the second stressed portion.

### Claim 8 (depends on 7)

The device of claim 7, further comprising:
a first source and a first drain in the first stressed portion;
a first channel region separating the first source and the first drain;
a second source and a second drain in the second stressed portion; and
a second channel region separating the second source and the second drain.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first source and the first drain are a raised source and a raised drain, respectively.

### Claim 10

A device, comprising:
a substrate;
a first semiconductor layer on the substrate, the first semiconductor layer having a first portion and a second portion adjacent to the first portion, the second portion including a first semiconductor material and being thinner than the first portion; and
a second semiconductor layer on the second portion of the first semiconductor layer, the second semiconductor layer including a second semiconductor material.

### Claim 11 (depends on 10)

The device of claim 10, wherein a surface of the first portion of the first semiconductor layer being coplanar with a surface of the second semiconductor layer.

### Claim 12 (depends on 10)

The device of claim 10, further comprising:
a first trench isolation region extending through an insulating layer on the substrate and into the substrate, the first trench isolation region separating the first portion of the first semiconductor layer and the second semiconductor layer; and
a second trench isolation region extending through the insulating layer and into the substrate, the second semiconductor layer extending between the first trench isolation region and the second trench isolation region.

### Claim 13 (depends on 12)

The device of claim 12, further comprising a third trench isolation region extending through the insulating layer and into the substrate, the first portion of the first semiconductor layer extending between the first trench isolation region and the third trench isolation region.

### Claim 14 (depends on 10)

The device of claim 10, wherein the second portion of the first semiconductor layer is thinner than the second semiconductor layer.

### Claim 15 (depends on 10)

The device of claim 10, further comprising:
a first source and a first drain in the first portion of the first semiconductor layer;
a first channel region separating the first source and the first drain;
a first gate stack on the first channel region;
a second source and a second drain in the second semiconductor layer;
a second channel region separating the second source and the second drain; and
a second gate stack on the second channel region.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first source and the first drain are a raised source and a raised drain, respectively.

### Claim 17

A device, comprising:
a substrate having a first location and a second location adjacent to the first location;
a first semiconductor layer on the substrate at the first location, the first semiconductor layer including a first semiconductor material;
a second semiconductor layer on the substrate at the second location;
a third semiconductor layer that is between the substrate and the second semiconductor layer at the second location; and
a fourth semiconductor layer on the second semiconductor layer at the second location, the fourth semiconductor layer including a second semiconductor material.

### Claim 18 (depends on 17)

The device of claim 17, further comprising:
a first trench isolation region extending through an insulating layer on the substrate and into the substrate, the first trench isolation region separating the first semiconductor layer and the second semiconductor layer; and
a second trench isolation region extending through the insulating layer and into the substrate, the first semiconductor layer extending between the first trench isolation region and the second trench isolation region.

### Claim 19 (depends on 18)

The device of claim 18, further comprising a third trench isolation region extending through the insulating layer and into the substrate, the second, third, and fourth semiconductor layers extending between the first trench isolation region and the third trench isolation region.

### Claim 20 (depends on 17)

The device of claim 17, wherein the third semiconductor layer is thinner than the second semiconductor layer.

### Claim 21 (depends on 17)

The device of claim 17, wherein the third semiconductor layer is thinner than the first semiconductor layer.