# US 2018/0323299 A1 · Silicon carbide semiconductor device and manufacturing method for the same

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- Number: US 2018/0323299 A1
- Document ID: US20180323299A1
- Status: Published application
- Kind: A1
- Application number: 15/768,251
- Filed: 2016-09-13
- Published: 2018-11-08
- Earliest claimed: 2015-11-12
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Takaaki TOMINAGA; Shiro HINO
- Web page: https://patentgrep.com/patent/US20180323299A1

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 30/662: {having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region}
- H10D 30/665: {having edge termination structures}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10P 30/22: using masks
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A silicon carbide semiconductor device includes: a pair of first well regions separated by distance W1 in surface layer portions of a silicon carbide drift layer and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer; a pair of second well regions provided adjacent to bottom faces of the first well regions, separated by distance W2 larger than the distance W1 by 0.8 μm or more, and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer from 1.1 times to 4.2 times lower than the first well regions; and a highly concentrated JFET region provided between the pair of first well regions and between the pair of second well regions and having n-type impurity concentration higher than that of the silicon carbide drift layer and lower than p-type impurity concentration or the second well regions.

## Claims

### Claim at position 1

1-9. (canceled)

### Claim 10

A silicon carbide semiconductor device comprising:
a silicon carbide semiconductor substrate;
a silicon carbide drift layer of a first conductive type provided on the silicon carbide semiconductor substrate;
first well regions of a second conductive type provided in surface layer portions of the silicon carbide drift layer;
second well regions of the second conductive type provided adjacent to respective bottom faces of the first well regions;
source regions of the first conductive type provided in respective surface layer portions of the first well regions;
a highly concentrated JFET region of the first conductive type formed deeper than the second well regions and provided between the first well regions as well as between the second well regions, wherein an impurity concentration of the first conductive type is larger than that of the silicon carbide drift layer;
a gate insulating film provided on a top face of the highly concentrated JFET region, top faces of the first well regions, and top faces of the source regions in contact with the highly concentrated JFET region, the first well regions, and the source regions; and
a gate electrode provided on and in contact with the gate insulating film,
wherein a separation distance W2 of the second well regions is larger than a separation distance W1 of the first well regions by 0.8 μm or more and an impurity concentration the second conductive type in the first well regions is 1.1 times to 4.2 times an impurity concentration of the second conductive type in the second well region.

### Claim 11 (depends on 10)

The silicon carbide semiconductor device according to claim 10, wherein the impurity concentration of the second conductive type in the first well regions is 1.8 times to 3.6 times the impurity concentration of the second conductive type in the second well regions.

### Claim 12 (depends on 10)

The silicon carbide semiconductor device according to claim 10, wherein a separation distance between the source regions is 0.9 times to 1.1 times the separation distance between the second well regions.

### Claim 13 (depends on 10)

The silicon carbide semiconductor device according to claim 10, wherein a width of the highly concentrated JFET region is equal to the separation distance W2 at a depth where the second well regions is located.

### Claim 14 (depends on 10)

The silicon carbide semiconductor device according to claim 10, wherein the first well regions have a thickness in a range from 0.5 μm to 3 μm.

### Claim 15 (depends on 10)

The silicon carbide semiconductor device according to claim 10, wherein the second well regions have a peak value of the impurity, concentration of the second conductive type located at a depth from 0.6 μm to 4 μm from a top face of the silicon carbide drift layer.

### Claim 16 (depends on 10)

The silicon carbide semiconductor device according to claim 10, further comprising a breakdown voltage retention region of the second conductive type at a chip end portion, having the impurity concentration of the second conductive type being equal to that of the second well regions.

### Claim 17 (depends on 10)

The silicon carbide semiconductor device according to claim 10, further comprising third well regions of the second conductive type provided adjacent to respective bottom faces of the second well regions, wherein, a separation distance W3 between the third well regions is larger than the separation distance W2 and the second well regions have the impurity concentration, of the second conductive type larger than that of the third well regions.

### Claim 18

A manufacturing method for a silicon carbide semiconductor device, comprising:
a first crystal-growing a silicon carbide drill layer of a first conductive type on a silicon carbide semiconductor substrate;
a second forming a first implantation mask on the silicon carbide drift layer and implanting impurity ions of a second conductive type in the silicon carbide drift layer to form a first well region of the second conductive type in a surface layer portion of the silicon carbide drift layer;
a third forming a second implantation mask whose width is larger than the first implantation mask on the silicon carbide drift layer, and implanting impurity ions of the second conductive type in the silicon carbide drift layer to form a second well region of the second conductive type on a region adjacent to a bottom face of the first well region;
a fourth forming a source region of the first conductive type by implanting impurity ions of the first conductive type in a surface layer portion of the first well region;
a fifth implanting impurity ions of the first conductive type into a region ranging from a top face of the silicon carbide drift layer down to a depth larger than the depth of the first well region to form a highly concentrated JFET region of the first conductive type,
a sixth forming a gate insulation film on a top face of the first well region, a top face of the source region, and a top face of the highly concentrated JFET region; and
a seventh forming a gate electrode on the gate insulation film.

### Claim 19 (depends on 18)

The manufacturing method for the silicon carbide semiconductor device according to claim 18, wherein the source region is formed by implanting impurity ions of the first conductive type in a state where the second implantation mask is formed on the silicon carbide drift layer.

### Claim 20 (depends on 18)

The manufacturing method for the silicon carbide semiconductor device according to claim 18, wherein the first implantation mask is formed by processing the second implantation mask to be small in width.

### Claim 21 (depends on 18)

The manufacturing method for the silicon carbide semiconductor device according to claim 18, wherein, in the third forming, impurity ions, of the second conductive type are implanted also in a chip end portion to form, along with the second well, region, a breakdown voltage retention region of the second conductive type at the chip end portion.