# US 2018/0323296 A1 · Method for manufacturing a hemt transistor and hemt transistor with improved electron mobility

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- Number: US 2018/0323296 A1
- Document ID: US20180323296A1
- Status: Published application
- Kind: A1
- Application number: 16/020,807
- Filed: 2018-06-27
- Published: 2018-11-08
- Earliest claimed: 2015-11-12
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics S.R.L.
- Inventors: Ferdinando Iucolano; Andrea Severino; Maria Concetta Nicotra; Alfonso Patti
- Web page: https://patentgrep.com/patent/US20180323296A1

## CPC

- H10D 30/4735: {having delta-doped or planar-doped donor layers}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4732: {using Group III-V semiconductor material}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3416: {Nitrides}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

## Claims

### Claim 1

A transistor, comprising:
a semiconductor body;
a first dielectric layer on the semiconductor body;
an opening extending through the first dielectric layer, the opening having sidewalls and a bottom surface;
an interface layer on the sidewalls of the opening;
a second dielectric layer formed on the interface layer;
a gate electrode positioned at least partially in the opening and on the second dielectric layer;
a source contact having a first portion and a second portion, the first portion of the source contact extending through the first dielectric layer and into the semiconductor body in a first direction, the second portion of the source contact extending on the second dielectric layer in a second direction that is transverse to the first direction; and
a drain contact having a first portion and a second portion, the first portion of the drain contact extending through the first dielectric layer and into the semiconductor body in the first direction, the second portion of the drain contact extending on the second dielectric layer in the second direction.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the semiconductor body includes at least a first semiconductor layer and a second semiconductor layer.

### Claim 3 (depends on 2)

The transistor of claim 2, wherein the source contact and the drain contact extend through the second semiconductor layer and into the first semiconductor layer.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the gate electrode extends to a first depth, and the source contact and the drain contact extend to a second depth that is greater than the first depth.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein the gate electrode extends to a first depth, and the source contact and the drain contact extend to a second depth that is less than the first depth.

### Claim 6 (depends on 1)

The transistor of claim 1, wherein the gate electrode has a first portion and a second portion, the first portion of the gate electrode extending in the first direction, the second portion of the drain contact extending on the second dielectric layer in the second direction.

### Claim 7

A transistor, comprising:
a first semiconductor layer;
a second semiconductor layer on the first semiconductor layer;
a first dielectric layer on the second semiconductor layer;
an opening extending in a first direction through the first dielectric layer, the opening having sidewalls and a bottom surface;
an interface layer on the sidewalls of the opening;
a second dielectric layer formed on the interface layer;
a gate electrode positioned at least partially in the opening and on the second dielectric layer;
a source contact having a first portion extending through the second dielectric layer in the first direction; and
a drain contact having a first portion extending through the second dielectric layer in the first direction.

### Claim 8 (depends on 7)

The transistor of claim 7, wherein the gate electrode extends to a first depth, and the source contact and the drain contact extend to a second depth that is greater than the first depth.

### Claim 9 (depends on 7)

The transistor of claim 7, wherein the source contact includes a second portion extending on the second dielectric layer in a second direction that is transverse to the first direction; and
wherein the drain contact includes a second portion extending on the second dielectric layer in the second direction.

### Claim 10 (depends on 7)

The transistor of claim 7, wherein the interface layer is of a III-V semiconductor material.

### Claim 11 (depends on 7)

The transistor of claim 7, wherein the source contact is spaced apart from a first side of the gate electrode and the drain contact is spaced apart from a second side of the gate electrode.

### Claim 12 (depends on 7)

The transistor of claim 7, wherein the source contact and the drain contact abut the second dielectric layer.

### Claim 13 (depends on 7)

The transistor of claim 7, wherein the source contact and the drain contact abut the interface layer.

### Claim 14

A transistor, comprising:
a first semiconductor layer;
a second semiconductor layer on the first semiconductor layer;
a first dielectric layer on the second semiconductor layer;
an opening extending in a first direction into the first semiconductor layer through the first dielectric layer and the second semiconductor layer, the opening having sidewalls and a bottom surface;
an interface layer on the sidewalls of the opening;
a second dielectric layer formed on the interface layer;
a gate electrode positioned at least partially in the opening and on the second dielectric layer;
a source contact having a first portion extending through the second dielectric layer in the first direction; and
a drain contact having a first portion extending through the second dielectric layer in the first direction.

### Claim 15 (depends on 14)

The transistor of claim 14, wherein the gate electrode extends to a first depth, and the source contact and the drain contact extend to a second depth that is greater than the first depth.

### Claim 16 (depends on 14)

The transistor of claim 14, wherein the gate electrode extends to a first depth, and the source contact and the drain contact extend to a second depth that is less than the first depth.

### Claim 17 (depends on 14)

The transistor of claim 14, wherein the opening extends through the first semiconductor layer.

### Claim 18 (depends on 14)

The transistor of claim 14, wherein the gate electrode has a first portion and a second portion, the first portion of the gate electrode extending in the first direction in the opening, the second portion of the gate electrode extending on the second dielectric layer in a second direction that is transverse to the first direction.

### Claim 19 (depends on 14)

The transistor of claim 14, wherein the source contact includes a second portion extending on the second dielectric layer in a second direction that is transverse to the first direction; and
wherein the drain contact includes a second portion extending on the second dielectric layer in the second direction.

### Claim 20 (depends on 19)

The transistor of claim 19, further comprising:
a substrate; and
a third semiconductor layer arranged between the substrate and the first semiconductor layer, wherein the opening extends into the third semiconductor layer.