# US 2018/0323293 A1 · Method for manufacturing a bipolar junction transistor

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- Number: US 2018/0323293 A1
- Document ID: US20180323293A1
- Status: Published application
- Kind: A1
- Application number: 16/023,418
- Filed: 2018-06-29
- Published: 2018-11-08
- Earliest claimed: 2016-05-02
- Assignees: Infineon Technologies Dresden GmbH
- Applicants: Infineon Technologies Dresden GMBH
- Inventors: Dirk MANGER; Stefan TEGEN
- Web page: https://patentgrep.com/patent/US20180323293A1

## CPC

- H10D 10/891: {comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors}
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 12/031: {of IGBTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D 62/138: {Pedestal collectors}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments provide a method for manufacturing a bipolar junction transistor, comprising: providing a semiconductor substrate comprising a buried layer of a first conductive type; doping the semiconductor substrate in a collector implant region, to obtain a collector implant of the first conductive type extending parallel to a surface of the semiconductor substrate and from the surface of the semiconductor substrate to the buried layer; providing a base layer of a second conductive type on the surface of the semiconductor substrate, the base layer covering the collector implant; providing a sacrificial emitter structure on the base layer, wherein a projection of an area of the sacrificial emitter structure is enclosed by an area of the collector implant; and partially counter doping the collector implant through an area of the base layer surrounding an area of the base layer that is covered by the sacrificial emitter structure.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A bipolar transistor, comprising:
a collector of a first conductive type;
a base layer of a second conductive type arranged above the collector;
an emitter of the first conductive type arranged above the base layer,
the collector being self-aligned to the emitter;
an emitter isolation layer laterally surrounding the emitter; and
a base link laterally connected to the base layer and extending lateral to the base layer,
the base link being vertically connected to a portion of the base layer and extending above the base layer, and
the base link being laterally connected to the emitter isolation layer.

### Claim 22 (depends on 21)

The bipolar transistor according to claim 21, further comprising:
a stop layer on the emitter and the base link.

### Claim 23 (depends on 22)

The bipolar transistor according to claim 22, wherein the stop layer is a SiN layer.

### Claim 24 (depends on 21)

The bipolar transistor according to claim 21, further comprising:
an emitter contact contacting the emitter, and
base contacts contacting the base link.

### Claim 25 (depends on 21)

The bipolar transistor according to claim 21, wherein the emitter has zero overlap with the base link.

### Claim 26

A method comprising:
providing a collector of a first conductive type;
arranging a base layer of a second conductive type above the collector;
providing an emitter of the first conductive type above the base layer,
the collector being self-aligned with the emitter;
surrounding the emitter with an emitter isolation layer; and
laterally connecting a base link to the base layer,
the base link extending lateral to the base layer,
the base link being vertically connected to a portion of the base layer and extending above the base layer, and
the base link being laterally connected to the emitter isolation layer.

### Claim 27 (depends on 26)

The method according to claim 26, wherein arranging the base layer comprises epitaxially growing the base layer on a surface of a semiconductor substrate at least in an area adjacent to the collector.

### Claim 28 (depends on 26)

The method according to claim 26, further comprising:
removing a sacrificial emitter to obtain an emitter window; and
where providing the emitter includes:
providing an emitter layer of the first conductive type in the emitter window to obtain the emitter.

### Claim 29 (depends on 28)

The method according to claim 28, wherein the emitter layer is provided such that an overfill of the emitter window is achieved.

### Claim 30 (depends on 28)

The method according to claim 28, wherein the emitter layer has a minimum thickness of 60 nm.

### Claim 31 (depends on 28)

The method according to claim 28, wherein the emitter layer has a width equal to 90 nm.

### Claim 32 (depends on 28)

The method according to claim 28, wherein providing the emitter includes:
partially removing the emitter layer to obtain the emitter in the emitter window.

### Claim 33 (depends on 28)

The method according to claim 28, wherein providing the emitter includes:
partially removing the emitter layer at least up to the base link to obtain the emitter in the emitter window.

### Claim 34 (depends on 26)

The method according to claim 26, further comprising:
providing a stop layer for contact hole etch on the emitter and the base link.

### Claim 35 (depends on 34)

The method according to claim 34, wherein the stop layer is a SiN layer.

### Claim 36 (depends on 26)

The method according to claim 26, further comprising:
providing base contacts contacting the base link.

### Claim 37 (depends on 36)

The method according to claim 36, wherein the base contacts are metal.

### Claim 38 (depends on 26)

The method according to claim 26, further comprising:
providing an emitter contact contacting the emitter.

### Claim 39 (depends on 38)

The method according to claim 38, wherein the emitter contact is metal.

### Claim 40 (depends on 26)

The method according to claim 26, wherein the emitter has zero overlap with the base link.