# US 2018/0323288 A1 · Finfet with epitaxial source and drain regions and dielectric isolated channel region

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- Number: US 2018/0323288 A1
- Document ID: US20180323288A1
- Status: Published application
- Kind: A1
- Application number: 16/030,359
- Filed: 2018-07-09
- Published: 2018-11-08
- Earliest claimed: 2014-05-01
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: KANGGUO CHENG; RAMACHANDRA DIVAKARUNI; ALI KHAKIFIROOZ; ALEXANDER REZNICEK; SOON-CHEON SEO
- Web page: https://patentgrep.com/patent/US20180323288A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0217: {forming self-aligned punch-through stoppers or threshold implants under gate regions}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

## Claims

### Claim 1

A method comprising:
removing exposed portions of at least one fin structure;
forming a sacrificial spacer on a sidewall of a gate structure present on remaining portion of the at least one fin structure;
removing exposed portions of an underlying insulator layer to provide a pedestal of insulating material exposing a portion of at least one semiconductor layer;
forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer, the first epitaxial material layer contacting the sacrificial spacer; and
forming a second epitaxial material layer in a space provided by said removing of the sacrificial spacer to provide source and drain regions.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising forming a gate sidewall spacer directly on the sidewall of the gate structure prior to the removing of the exposed portions of the insulator layer, wherein said forming the sacrificial spacer over the sidewall of the gate structure comprises forming the sacrificial spacer directly on the gate sidewall spacer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the at least one semiconductor layer comprises a punch-through layer and a semiconductor substrate, wherein the punch-through layer is present between the insulating layer and the semiconductor substrate.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the punch-through layer is a doped layer with a dopant opposite to a dopant that dictates the conductivity type of the source and drain regions.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the second epitaxial material layer contacts the pedestal of insulating material and does not contact the at least one semiconductor layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the second epitaxial material layer separates the first epitaxial material layer from contacting the at least one fin structure.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the sacrificial spacer that is present on the sidewall of the gate structure has a base that is in contact with the pedestal of insulting material.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the first epitaxial material layer is epitaxially grown from a surface of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherien the second epitaxial material layer is epitaxially grown from a surface of the sidewall of the at least one fin structure and a surface of the first epitaxial material layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein an interface between the first epitaxial layer of the source and drain region structures and the channel region is substantially free of defects.

### Claim 11

A method comprising:
removing end portions of the at least one fin structure;
removing exposed portions of the insulator layer to provide a pedestal of insulating material;
forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer; and
forming a second epitaxial material layer in a space provided by removing a sacrificial spacer to provide source and drain regions.

### Claim 12 (depends on 11)

The method according to claim 11, further comprising forming a gate sidewall spacer directly on the sidewall of a gate structure prior to the removing of the exposed portions of the insulator layer, and forming a sacrificial spacer over the sidewall of the gate structure directly on the gate sidewall spacer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the at least one semiconductor layer comprises a punch-through layer and a semiconductor substrate, wherein the punch-through layer is present between the insulating layer and the semiconductor substrate.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the punch-through layer is a doped layer with a dopant opposite to a dopant that dictates the conductivity type of the source and drain regions.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the second epitaxial material layer contacts the pedestal of insulating material and does not contact the at least one semiconductor layer.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the second epitaxial material layer separates the first epitaxial material layer from contacting the at least one fin structure.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the sacrificial spacer that is present on the sidewall of the gate structure has a base that is in contact with the pedestal of insulting material.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the first epitaxial material layer is epitaxially grown from a surface of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the second epitaxial material layer is epitaxially grown from a surface of the sidewall of the at least one fin structure and a surface of the first epitaxial material layer.

### Claim 20 (depends on 12)

The method according to claim 12, wherein an interface between the first epitaxial layer of the source and drain region structures and the channel region is substantially free of defects.