# US 2018/0323285 A1 · Lateral Transistors and Methods with Low-Voltage-Drop Shunt to Body Diode

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- Number: US 2018/0323285 A1
- Document ID: US20180323285A1
- Status: Published application
- Kind: A1
- Application number: 15/975,284
- Filed: 2018-05-09
- Published: 2018-11-08
- Earliest claimed: 2012-02-13
- Assignees: MaxPower Semiconductor, Inc.
- Applicants: MaxPower Semiconductor Inc.
- Inventors: Mohamed N. Darwish; Jun Zeng; Richard A. Blanchard
- Web page: https://patentgrep.com/patent/US20180323285A1

## CPC

- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 12/441: {Vertical IGBTs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

## Claims

### Claim at position 1

1-39. (canceled)

### Claim 40

A power semiconductor device, comprising:
a first and second group of laterally-gated transistors integrated on a single semiconductor die, each said laterally-gated transistor having a first-conductivity-type source region, and a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, and a vertically-extended conduction region connecting a drain region to a drain extension region which is adjacent to said lateral channel;
wherein the threshold voltages of said first group of laterally-gated transistors are lower than the threshold voltages of said second group of laterally-gated transistors;
wherein the vertically-extended conduction region of at least each said second laterally-gated transistor is provided by fixed electrostatic charges in the walls of a trenched field plate, which invert a portion of said body region; and
shielding shapes interposed between the gate electrodes of said laterally-gated transistors.

### Claim 41 (depends on 40)

The device of claim 40, wherein said first conductivity type is N type.

### Claim 42 (depends on 40)

The device of Claim 40 35, wherein said semiconductor die is made of silicon.

### Claim 43

A power semiconductor device, comprising:
a first and a second laterally-gated transistor both having a portion of a first-conductivity-type source region, a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, a first-conductivity-type drain extension region connecting said lateral channel to a common drain electrode, and a vertically-extended source extension region connecting said source region to a common source electrode on the backside of the device;
wherein both said gate electrodes are electrically separate portions of a single thin film layer;
wherein the threshold voltage of said first laterally-gated transistor is less than the threshold voltage of said second laterally-gated transistor;
wherein the gate electrode of said first laterally-gated transistor, but not the gate electrode of said second laterally-gated transistor, is connected to said common source electrode.

### Claim 44 (depends on 43)

The device of claim 43, wherein the lateral channel of said first laterally-gated transistor has a shorter lateral extent than does the lateral channel of said second laterally-gated transistor.

### Claim 45 (depends on 43)

The device of claim 43, further comprising impurities implanted in the lateral channel of said first laterally-gated transistor which decrease the threshold voltage of said first laterally-gated transistor.

### Claim 46 (depends on 43)

The device of claim 43, wherein said laterally-gated transistors both have a first-conductivity-type lateral source extension region laterally connecting said source region to said lateral channel

### Claim 47

A power semiconductor device, comprising:
a first and a second laterally-gated transistor both having a portion of a first-conductivity-type source region, a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, a first-conductivity-type drain extension region connecting said lateral channel to a common drain electrode, and a vertically-extended source extension region connecting said source region to a common source electrode on the backside of the device;
wherein both said gate electrodes are electrically separate portions of a single thin film layer;
wherein the threshold voltage of said first laterally-gated transistor is less than the threshold voltage of said second laterally-gated transistor;
wherein the gate electrode of said first laterally-gated transistor, but not the gate electrode of said second laterally-gated transistor, is connected to said common source electrode; and
wherein said vertically-extended source extension regions are a single common region which laterally separates said first and second laterally-gated transistors.

### Claim 48 (depends on 43)

The device of claim 43, further comprising a shielding shape interposed between said gate electrodes.

### Claim 49 (depends on 43)

The device of claim 43, wherein said first conductivity type is N type.