# US 2018/0323282 A1 · Power device with high aspect ratio trench contacts and submicron pitches between trenches

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- Number: US 2018/0323282 A1
- Document ID: US20180323282A1
- Status: Published application
- Kind: A1
- Application number: 16/020,699
- Filed: 2018-06-27
- Published: 2018-11-08
- Earliest claimed: 2015-01-23
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha & Omega Semiconductor, Incorporated
- Inventors: Wenjun Li; Paul Thorup; Hong Chang; Yeeheng Lee; Yang Xiang; Jowei Dun; Hongyong Xue; Yiming Gu
- Web page: https://patentgrep.com/patent/US20180323282A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

## Claims

### Claim 1

A semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area wherein the semiconductor power device further comprising:
a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches covered by a high density plasma (HDP) insulation layer wherein the HDP insulation layer vertically sticks out above the gate trenches;
spacers attached to a top portion of the HDP insulation layer above the gate trenches and exposing a top surface of mesa areas of the semiconductor substrate between the gate trenches; and
each of the mesa areas between the gate trenches having a deep contact trench vertically aligned with the spacers and extending vertically below a top surface of the conductive materially partially filling the trench gate wherein the recessed contact trenches are filled with a source/body contact material.

### Claim 2 (depends on 1)

The semiconductor power device of claim 1 wherein:
the spacers attached to the top portion of the HDP insulation layer above the gate trenches are configured to define mesa-center areas disposed substantially in a middle portion of the mesa areas for etching the deep contact trenches below the mesa-center areas.

### Claim 3 (depends on 2)

The semiconductor power device of claim 2 wherein:
the deep contact trenches opened vertically in the semiconductor substrate below the mesa-center areas are filled a metal contact.

### Claim 4 (depends on 3)

The semiconductor power device of claim 3 further comprising:
a contact implant region disposed in the semiconductor substrate below a bottom surface of each of the deep contact trenches.

### Claim 5 (depends on 3)

The semiconductor power device of claim 3 further comprising:
a source region disposed in the semiconductor substrate surrounding and directly contacting each of the deep contact trenches filled with the source/body contact material.

### Claim 6 (depends on 5)

The semiconductor power device of claim 5 further comprising:
a body region in the semiconductor substrate surrounding each of the deep contact trenches between the gate trenches and encompassing the source regions.

### Claim 7 (depends on 1)

The semiconductor power device of claim 1 wherein:
the spacers are low temperature oxide (LTO) layer attached to the portion of the HDP insulation layer above the gate trenches.

### Claim 8 (depends on 6)

The semiconductor power device of claim 6 wherein:
the body regions extend over regions of the semiconductor substrate between the gate trenches with the deep contact trench penetrating through the source regions contacting the contact implant regions disposed below the bottom surface of the contact trenches disposed in the body regions.

### Claim 9 (depends on 8)

The semiconductor power device of claim 8 further comprising:
a source metal layer disposed on top of the HDP layer and the contact trenches in contact with the conductive material filling the contact trenches for electrically connected to the source regions and body regions.

### Claim 10 (depends on 8)

The semiconductor power device of claim 8 further comprising:
a body clamping layer (BCL) of the same conductivity type as the body region extending vertically below a bottom surface of the gate trenches in a peripheral area of the active cell area.

### Claim 11 (depends on 3)

The semiconductor power device of claim 3 wherein:
the contact trenches have a width substantially between 0.1 to 0.15 micrometers.

### Claim 12 (depends on 1)

The semiconductor power device of claim 1 wherein:
the gate trenches have a width approximately 0.25 micrometers and a distance between adjacent gate trenches having a pitch approximately 0.5 micrometers.

### Claim 13 (depends on 1)

The semiconductor power device of claim 1 further comprising:
a source metal layer covering over the active cell area and a gate metal layer covering over a termination area wherein the source metal and the gate metal are separated by a gap substantially aligned with one of the spacers adjacent one of the gate trenches functioning as a gate pickup trench disposed on an edge of the active cell area.