# US 2018/0323281 A1 · Forming a uniform inner spacer for a vertical transport fin field effect transistor

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- Number: US 2018/0323281 A1
- Document ID: US20180323281A1
- Status: Published application
- Kind: A1
- Application number: 15/586,830
- Filed: 2017-05-04
- Published: 2018-11-08
- Earliest claimed: 2017-05-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Juntao Li; Peng Xu; Jingyun Zhang
- Web page: https://patentgrep.com/patent/US20180323281A1

## CPC

- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/837: {comprising vertical IGFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a vertical transport fin field effect transistor (VT FinFET), including, forming a plurality of vertical fins on a substrate, forming a sacrificial liner on at least two of the plurality of vertical fins, forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins, and removing a portion of the sacrificial liner to form an 1-shaped channel adjacent to each of the at least two of the plurality of vertical fins.

## Claims

### Claim 1

A method of forming a vertical transport fin field effect transistor (VT FinFET), comprising:
forming a plurality of vertical fins on a substrate;
forming a sacrificial liner on at least two of the plurality of vertical fins;
forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins; and
removing a portion of the sacrificial liner to form an L-shaped channel adjacent to each of the at least two of the plurality of vertical fins.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an inner spacer layer on the surface of the substrate, wherein the inner spacer layer fills the L-shaped channel adjacent to each of the at least two of the plurality of vertical fins.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
removing a portion of the inner spacer layer to form L-shaped inner spacers in the L-shaped channels.

### Claim 4 (depends on 3)

The method of claim 3, wherein the L-shaped inner spacers have a height in the range of about 2 nm to about 7 nm along the at least two of the plurality of vertical fins.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a bottom source/drain layer at a surface of a substrate, wherein the plurality of vertical fins are on the bottom source/drain layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sidewall spacers have a thickness in the range of about 5 nm to about 15 nm.

### Claim 7 (depends on 1)

The method of claim 1, wherein the sacrificial liner has a thickness in the range of about 1 nm to about 4 nm.

### Claim 8 (depends on 1)

The method of claim 1, further comprising.
forming a dielectric fill layer on the substrate and vertical fins, and etching back the dielectric fill layer and sidewall spacers to form outer spacers on the L-shaped inner spacers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the sacrificial liner is silicon borocarbonitride (SiBCN).

### Claim 10

A method of forming a vertical transport fin field effect transistor (VT FinFET), comprising:
forming a plurality of vertical fins on a substrate;
forming a sacrificial liner on at least two of the plurality of vertical fins, wherein the sacrificial liner is formed by a conformal deposition;
forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins;
removing a portion of the sacrificial liner to form an L-shaped channel adjacent to each of the at least two of the plurality of vertical fins; and
removing a portion of the inner spacer layer to form L-shaped inner spacers in the L-shaped channels.

### Claim 11 (depends on 10)

The method of claim 10, wherein the sacrificial liner is silicon borocarbonitride (SiBCN).

### Claim 12 (depends on 11)

The method of claim 11, wherein the sacrificial liner has a thickness in the range of about 1 nm to about 4 nm.

### Claim 13 (depends on 12)

The method of claim 12, wherein the sidewall spacers are silicon oxide (SiO).

### Claim 14 (depends on 12)

The method of claim 12, wherein the sidewall spacers have a thickness in the range of about 5 nm to about 15 nm.

### Claim 15

A vertical transport fin field effect transistor (VT FinFET), comprising:
a plurality of vertical fins on a substrate;
an L-shaped inner spacer adjacent to each of the at least two of the plurality of vertical fins;
an outer spacer on each of the L-shaped inner spacers; and
a gate structure on the outer spacers and the L-shaped inner spacers.

### Claim 16 (depends on 15)

The vertical transport fin field effect transistor of claim 15, wherein the L-shaped inner spacers are silicon borocarbonitride (SiBCN).

### Claim 17 (depends on 15)

The vertical transport fin field effect transistor of claim 15, wherein the L-shaped inner spacers have a height in the range of about 2 nm to about 7 nm along the at least two of the plurality of vertical fins.

### Claim 18 (depends on 17)

The vertical transport fin field effect transistor of claim 17, wherein a top surface of the outer spacer is higher than the height of an adjacent L-shaped inner spacer.

### Claim 19 (depends on 18)

The vertical transport fin field effect transistor of claim 18, wherein the outer spacer is silicon oxide (SiO).

### Claim 20 (depends on 19)

The vertical transport fin field effect transistor of claim 19, further comprising a dielectric isolation region between the at least two of the plurality of vertical fins.