# US 2018/0323277 A1 · Fin-fet devices and fabrication methods thereof

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- Number: US 2018/0323277 A1
- Document ID: US20180323277A1
- Status: Published application
- Kind: A1
- Application number: 15/971,109
- Filed: 2018-05-04
- Published: 2018-11-08
- Earliest claimed: 2017-05-05
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei ZHOU
- Web page: https://patentgrep.com/patent/US20180323277A1

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 86/011: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a Fin-FET device includes forming a plurality of discrete fin structures on a substrate which includes a first device region and a second device region, forming a plurality of dummy gate electrodes across the fin structures, and forming an interlayer dielectric layer exposing the dummy gate electrodes on a portion of the fin structures exposed by the dummy gate electrodes, forming a first opening by removing each dummy gate electrode, forming an initial metal gate electrode in the first opening and between adjacent fin structures, and forming a second opening through the initial metal gate electrode. The initial metal gate electrode formed in the first device region is a first metal gate electrode, and the initial metal gate electrode formed in the second device region is a second metal gate electrode. The second opening separates the first metal gate electrode from the second metal gate electrode.

## Claims

### Claim 1

A method for fabricating a fin field-effect transistor (Fin-FET) device, comprising:
forming a plurality of discrete fin structures on a substrate, wherein the substrate includes a first device region and a second device region;
forming a plurality of dummy gate electrodes across the fin structures to cover a portion of top and sidewall surfaces of each fin structure;
forming an interlayer dielectric layer on a portion of the fin structures exposed by the dummy gate electrodes, wherein the interlayer dielectric layer exposes the dummy gate electrodes;
forming a first opening in the interlayer dielectric layer by removing each dummy gate electrode;
forming an initial metal gate electrode to fill up the first opening and on the substrate between adjacent fin structures; and
forming a second opening through the initial metal gate electrode and on the substrate, wherein;
a portion of the initial metal gate electrode formed in the first device region is a first metal gate electrode, and a portion of the initial metal gate electrode formed in the second device region is a second metal gate electrode, and
the second opening separates the first metal gate electrode in the first device region from the second metal gate electrode in the second device region.

### Claim 2 (depends on 1)

The method for fabricating the Fin-FET device according to claim 1, wherein:
along a direction perpendicular to an extending direction of the fin structures, a width of the second opening is in a range of approximately 50 Å to 100 Å.

### Claim 3 (depends on 2)

The method for fabricating the Fin-FET device according to claim 2, wherein:
the second opening is formed by a dry etching process.

### Claim 4 (depends on 3)

The method for fabricating the Fin-FET device according to claim 3, wherein parameters used in the dry-etching process include:
an etching gas containing a mixture of CF4, SF6, Cl2, and O2;
a flowrate of CF4 in a range of approximately 10 sccm to 500 sccm;
a flowrate of SF6 in a range of approximately 20 sccm and 300 sccm;
a flowrate of Cl2 in a range of approximately 6 sccm to 120 sccm;
a flow rate of O2 in a range of approximately 1 sccm to 90 sccm;
a process pressure in a range of approximately 1 mTorr to 350 mTorr; and
a process power in a range of approximately 100 W to 500 W.

### Claim 5 (depends on 1)

The method for fabricating the Fin-FET device according to claim 1, after forming the first opening and prior to forming the initial metal gate electrode, further including:
forming a high-k dielectric layer on the interlayer dielectric layer, and on bottom and sidewall surfaces of the first opening; and
forming a work function layer on the high-k dielectric layer.

### Claim 6 (depends on 1)

The method for fabricating the Fin-FET device according to claim 1, prior to forming the second opening, further including:
forming a cap layer on the initial metal gate electrode.

### Claim 7 (depends on 6)

The method for fabricating the Fin-FET device according to claim 6, wherein:
the cap layer is made of one or more of SiN8, SiCN, SiBN, SiCON, SiCN, and amorphous carbon.

### Claim 8 (depends on 1)

The method for fabricating the Fin-FET device according to claim 1, after forming the second opening, further including:
forming a dielectric layer to fill up the second opening.

### Claim 9 (depends on 8)

The method for fabricating the Fin-FET device according to claim 8, wherein:
the dielectric layer is made of a low-k dielectric material.

### Claim 10 (depends on 9)

The method for fabricating the Fin-FET device according to claim 9, wherein:
the dielectric layer is made of one or more of SiOx, SiNx, and SiON.

### Claim 11 (depends on 10)

The method for fabricating the Fin-FET device according to claim 10, wherein:
the dielectric layer is formed by a fluid chemical vapor deposition (CVD) process.

### Claim 12 (depends on 1)

The method for fabricating the Fin-FET device according to claim 1, prior to forming the plurality of dummy gate electrodes, further including:
forming an isolation structure on the substrate between neighboring fin structures, wherein:
the isolation structure covers a portion of the sidewall surfaces of each fin structure; and
a top surface of the isolation structure is lower than the top surfaces of the fin structures.

### Claim 13

A Fin-FET device, comprising:
a substrate including a first device region and a second device region;
a plurality of discrete fin structures formed on the substrate;
an initial metal gate electrode formed across the plurality of fin structure and covering a portion of top and sidewall surfaces of each fin structure in the first and second device regions; and
an interlayer dielectric layer formed on a portion of the fin structures exposed by the initial metal gate electrode, wherein the initial metal gate electrode contains an opening between adjacent fin structures in the first and second device regions.

### Claim 14 (depends on 13)

The Fin-FET device according to claim 13, wherein:
along a direction perpendicular to an extending direction of the fin structures, a width of the initial metal gate electrode on each fin structure is in a range of approximately 50 Å to 100 Å.

### Claim 15 (depends on 13)

The Fin-FET device according to claim 13, wherein:
a portion of the initial metal gate electrode formed in the first device region is a first metal gate electrode, and
a portion of the initial metal gate electrode formed in the second device region is a second metal gate electrode,
wherein the opening separates the first metal gate electrode in the first device region from the second metal gate electrode in the second device region.

### Claim 16 (depends on 13)

The Fin-FET device according to claim 13, further including:
a high-k dielectric layer formed under the initial metal gate electrode and on the fin structure; and
a work function layer formed on the high-k dielectric layer.

### Claim 17 (depends on 13)

The Fin-FET device according to claim 13, further including:
a cap layer formed on the initial metal gate electrode, wherein the cap layer is made of one or more of SiNx, SiCN, SiBN, SiCON, SiCN, and amorphous carbon.

### Claim 18 (depends on 13)

The Fin-FET device according to claim 13, further including:
a dielectric layer filling up the opening.

### Claim 19 (depends on 18)

The Fin-FET device according to claim 18, wherein:
the dielectric layer is made of one or more of SiOx, SiNx, and SiON.

### Claim 20 (depends on 13)

The Fin-FET device according to claim 13, further including:
an isolation structure formed on the substrate between neighboring fin structures, wherein:
the isolation structure covers a portion of the sidewall surfaces of each fin structure; and
a top surface of the isolation structure is lower than the top surfaces of the fin structures.