# US 2018/0323276 A1 · Method for forming a low-k spacer

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- Number: US 2018/0323276 A1
- Document ID: US20180323276A1
- Status: Published application
- Kind: A1
- Application number: 15/589,659
- Filed: 2017-05-08
- Published: 2018-11-08
- Earliest claimed: 2017-05-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsiu-Yu KANG; Hong-Wei CHEN
- Web page: https://patentgrep.com/patent/US20180323276A1

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/01: Manufacture or treatment
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/6338: {the reactions being activated by other means than plasma or thermal, e.g. photo-CVD}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6529: {by exposure to a gas or vapour}
- H10P 14/6532: {by exposure to a plasma}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 70/20: {Cleaning during device manufacture}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can he deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.

## Claims

### Claim 1

A method comprising:
forming a gate stack on a substrate, wherein the gate stack comprises an upper surface and a sidewall surface;
forming a first spacer on the upper surface and the sidewall surface of the gate stack;
forming a second spacer over the first spacer;
treating the second spacer with a plasma at a first temperature for a first period of time;
treating the second spacer with a gas at a second temperature for a second period of time; and
removing a portion of the first spacer and a portion of the second spacer formed over the upper surface of the gate stack.

### Claim 2 (depends on 1)

The method of claim 1, further comprising replacing the gate stack with a metal gate stack, wherein the metal gate stack is formed over a fin active region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the first spacer comprises depositing the first spacer with an atomic layer deposition (ALD) process.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first spacer comprises silicon (Si), oxygen (O), nitrogen (N), and carbon (C).

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming the second spacer comprises depositing the second spacer with an ALD process.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second spacer comprises silicon (Si), oxygen (O), and carbon (C).

### Claim 7 (depends on 1)

The method of claim 1, wherein the second spacer has a dielectric constant less than 4.0.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first spacer and the second spacer each has a thickness between 35 Å and 45 Å.

### Claim 9 (depends on 1)

The method of claim 1, wherein the plasma comprises a helium (He) plasma.

### Claim 10 (depends on 1)

The method of claim 1, wherein the gas comprises nitrogen (N2) or hydrogen (H2).

### Claim 11 (depends on 1)

The method of claim 1, wherein the second temperature is higher than the first temperature.

### Claim 12 (depends on 1)

The method of claim 1, wherein the gate stack comprises a metal layer and a dielectric layer.

### Claim 13

A method comprising:
forming a gate stack on a substrate, wherein the gate stack has an upper surface and a sidewall surface;
forming a native oxide on the sidewall surface of the gate stack;
depositing a first spacer with a first atomic layer deposition (ALD) process at a first temperature for a first period of time, wherein the first spacer covers the upper surface and the sidewall surface of the gate stack;
forming a second spacer over the first spacer, wherein the forming the second spacer comprises:
depositing the second spacer with a second ALD process at a second temperature for a second period of time;
treating the second spacer with a helium (He) plasma at a third temperature for a third period of time; and
annealing the second spacer with a nitrogen (N2) gas at a fourth temperature for a fourth period of time; and
removing a portion of the first spacer and a portion of the second spacer over the upper surface of the gate stack.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second spacer comprises silicon (Si), oxygen (O), and carbon (C).

### Claim 15 (depends on 13)

The method of claim 13, wherein the second spacer has a dielectric constant less than 4.0.

### Claim 16 (depends on 13)

The method of claim 13, wherein the first spacer and the second spacer each has a thickness between 35 Å and 45 Å.

### Claim 17

A method comprising:
forming a protruding structure on a substrate, wherein the protruding structure has an upper surface and a sidewall surface;
depositing a first spacer, wherein the first spacer covers the upper surface and the sidewall surface of the protruding structure;
depositing a second spacer over the first spacer;
treating the second spacer with a helium (He) plasma at a first temperature;
annealing the second spacer with a nitrogen (N2) gas at a second temperature; and
removing a portion of the first spacer and a portion of the second spacer formed over the upper surface of the protruding structure.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second spacer has a thickness between 35 Å and 45 Å and a dielectric constant less than 4.0.

### Claim 19 (depends on 17)

The method of claim 17, wherein the treating the second spacer with the He plasma comprises forming Si—O—Si—C cage-link bonds in the second spacer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the second spacer comprises silicon (Si), oxygen (O), and carbon (C).