# US 2018/0323272 A1 · Gate cut device fabrication with extended height gates

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- Number: US 2018/0323272 A1
- Document ID: US20180323272A1
- Status: Published application
- Kind: A1
- Application number: 16/033,759
- Filed: 2018-07-12
- Published: 2018-11-08
- Earliest claimed: 2017-01-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Andrew M. Greene; John R. Sporre; Peng Xu
- Web page: https://patentgrep.com/patent/US20180323272A1

## CPC

- H10D 64/01: Manufacture or treatment
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0614: {using processes wherein the final gate is made after the completion of the source and drain regions, e.g. gate-last processes using dummy gates}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/511: {for IGFETs}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods of forming semiconductor devices include forming a lower dielectric layer to a height below a height of a dummy gate hardmask disposed across multiple device regions. The dummy gate structure includes a dummy gate and a dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.

## Claims

### Claim 1

A method of forming semiconductor devices comprising:
forming a lower dielectric layer to a height below a height of a dummy gate hardmask disposed across multiple device regions, wherein the dummy gate structure includes a dummy gate and a dummy gate hardmask;
forming a protective layer on the dielectric layer to the height of the dummy gate hardmask; and
etching back the dummy gate hardmask to expose the dummy gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the lower dielectric layer comprises forming a dielectric fill to the height of the dummy gate hardmask and etching the dielectric fill back.

### Claim 3 (depends on 1)

The method of claim 1, wherein a thickness of the upper dielectric layer is greater than a thickness of the protective layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising converting the protective layer to an upper dielectric layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein converting the protective layer comprises oxidizing the protective layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the protective layer is formed from polysilicon and wherein converting the protective layer oxidizes the polysilicon to silicon dioxide.

### Claim 7 (depends on 4)

The method of claim 4, further comprising forming a sacrificial liner over the dummy gate after the dummy gate hardmask is etched back to protect the dummy gate from the conversion of the protective layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising etching away the sacrificial liner after converting the protective layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
removing the dummy gate in one or more barrier regions; and
forming a dielectric barrier in the one or more barrier regions

### Claim 10 (depends on 9)

The method of claim 9, further comprising replacing the dummy gate in regions outside the one or more barrier regions to form a plurality of final gates.

### Claim 11 (depends on 10)

The method of claim 10, wherein replacing the dummy gate comprises depositing dummy gate material to a height above a height of the original dummy gate hardmask.

### Claim 12

A method of forming semiconductor devices comprising:
forming a lower dielectric layer to a height below a height of a dummy gate hardmask disposed across multiple device regions, wherein the dummy gate structure includes a dummy gate and a dummy gate hardmask;
forming a protective layer on the dielectric layer to the height of the dummy gate hardmask;
etching back the dummy gate hardmask to expose the dummy gate;
converting the protective layer to an upper dielectric layer;
removing the dummy gate in one or more barrier regions; and
forming a dielectric barrier in the one or more barrier regions.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the lower dielectric layer comprises forming a dielectric fill to the height of the dummy gate hardmask and etching the dielectric fill back.

### Claim 14 (depends on 12)

The method of claim 12, wherein a thickness of the upper dielectric layer is greater than a thickness of the protective layer.

### Claim 15 (depends on 12)

The method of claim 12, wherein converting the protective layer comprises oxidizing the protective layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the protective layer is formed from polysilicon and wherein converting the protective layer oxidizes the polysilicon to silicon dioxide.

### Claim 17 (depends on 12)

The method of claim 12, further comprising forming a sacrificial liner over the dummy gate after the dummy gate hardmask is etched back to protect the dummy gate from the conversion of the protective layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising etching away the sacrificial liner after converting the protective layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising replacing the dummy gate in regions outside the one or more barrier regions to form a plurality of final gates.

### Claim 20 (depends on 19)

The method of claim 19, wherein replacing the dummy gate comprises depositing dummy gate material to a height above a height of the original dummy gate hardmask