# US 2018/0323269 A1 · Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a finfet device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0323269 A1 - Document ID: US20180323269A1 - Status: Published application - Kind: A1 - Application number: 15/585,865 - Filed: 2017-05-03 - Published: 2018-11-08 - Earliest claimed: 2017-05-03 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Inc. - Inventors: Yi Qi; Jianwei Peng; Hsien-Ching Lo; Kwan-Yong Lim; Hui Zhan - Web page: https://patentgrep.com/patent/US20180323269A1 ## CPC - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material ## Claims ### Claim 1 A method of forming a FinFET device, comprising: forming a gate around an initial fin structure and above a layer of insulating material, wherein said initial fin structure positioned in a source/drain region of said device comprises an exposed portion of said initial fin structure that is positioned above a level of an upper surface of said layer of insulating material, said exposed portion of said initial fin structure having a first size; performing a fin trimming process on said exposed portion of said initial fin structure so as to produce a reduced-size fin portion positioned above said upper surface of said layer of insulating material in said source/drain region of said device, said reduced-size fin portion having a second size that is less than said first size; forming a conformal epi semiconductor material on an upper surface and sidewall surfaces of said reduced-size fin portion, wherein said sidewall surfaces extend in a direction parallel to an axial length of said reduced-size fin portion; and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around said conformal epi semiconductor material. ### Claim 2 (depends on 1) The method of claim 1, wherein forming said conformal epi semiconductor material comprises forming a conformal and Gubstantially rectangular-shaped epi semiconductor material on said reduced-size fin portion. ### Claim 3 (depends on 1) The method of claim 1, wherein forming said conformal epi semiconductor material comprises forming said conformal epi semiconductor material on all surfaces of said reduced-size fin portion positioned above said upper surface of said layer of insulating material. ### Claim 4 (depends on 1) The method of claim 1, wherein forming said conformal epi semiconductor material comprises forming said conformal epi semiconductor material such that it encapsulates said reduced-size fin portion positioned above said upper surface of said layer of insulating material. ### Claim 5 (depends on 1) The method of claim 1, wherein, prior to performing said fin trimming process, said exposed portion of said initial fin structure in said source/drain region has a first height above said upper surface of said layer of insulating material and a first lateral width at a location that is approximately level with said upper surface of said layer of insulating material and wherein, after performing said fin trimming process, said reduced-size fin portion has a second height above said upper surface of said layer of insulating material and a second lateral width at a location adjacent an upper surface of said reduced-size fin portion, wherein said second height is less than said first height and said second width is less than said first width. ### Claim 6 (depends on 1) The method of claim 1, wherein forming said conductive source/drain contact structure comprises: forming a conformal metal silicide region on all exposed surfaces of said conformal epi semiconductor material; and forming a conductive material comprising a metal on said metal silicide region, all around said epi semiconductor material and above said layer of insulating material. ### Claim 7 (depends on 1) The method of claim 1, wherein, after performing said fin trimming process, said reduced-size fin portion is positioned adjacent a remaining portion of said initial fin structure positioned under said gate and wherein an upper surface of said reduced-size fin portion is at a level that is below a level of an upper surface of said remaining portion of said initial fin structure positioned under said gate. ### Claim 8 (depends on 7) The method of claim 7, wherein, after performing said fin trimming process, said reduced-size fin portion has a lateral width, in a gate-width direction of said device, at a location adjacent said upper surface of said reduced-size fin portion that is less than a lateral width, in said gate-width direction of said device, of said remaining portion of said initial fin structure positioned under said gate at a location adjacent an upper surface of said remaining portion of said initial fin structure positioned under said gate. ### Claim 9 (depends on 1) The method of claim 1, wherein said FinFET device is a P-type device and said initial fin structure comprises silicon and wherein forming said conformal epi semiconductor material comprises forming a conformal epi semiconductor material comprising silicon germanium (Si(1-x)Gex) on said reduced-size fin portion. ### Claim 10 (depends on 1) The method of claim 1, wherein said FinFET device is an N-type device and said initial fin structure comprises silicon and wherein forming said conformal epi semiconductor material comprises forming a conformal epi semiconductor material comprising N-doped silicon on said reduced-size fin portion. ### Claim 11 A method of forming a FinFET device, comprising: forming a gate around an initial fin structure and above a layer of insulating material, wherein said initial fin structure positioned in a source/drain region of said device comprises an exposed portion of said initial fin structure that is positioned above a level of an upper surface of said layer of insulating material, said exposed portion of said initial fin structure in said source/drain region having a first height above said upper surface of said layer of insulating material and a first lateral width at a location that is approximately level with said upper surface of said layer of insulating material; performing a fin trimming process on said exposed portion of said initial fin structure in said source/drain region of said device so as to produce a reduced-size fin portion positioned above said upper surface of said layer of insulating material, said reduced-size fin portion having a second height above said upper surface of said layer of insulating material and a second lateral width at a location adjacent an upper surface of said reduced-size fin portion, wherein said second height is less than said first height and said second width is less than said first width; forming a conformal and rectangular-shaped epi semiconductor material on an upper surface and sidewall surfaces of said reduced-size fin portion positioned above said upper surface of said layer of insulating material, wherein said sidewall surfaces extend in a direction parallel to an axial length of said reduced-size fin portion; and forming a conductive source/drain contact structure that is conductively coupled to and is wrapped around said conformal and rectangular-shaped epi semiconductor material. ### Claim 12 (depends on 11) The method of claim 11, wherein forming said conformal and rectangular-shaped epi semiconductor material comprises forming said conformal and rectangular-shaped epi semiconductor material such that it encapsulates said reduced-size fin portion positioned above said upper surface of said layer of insulating material. ### Claim 13 (depends on 11) The method of claim 11, wherein forming said conductive source/drain contact structure comprises: forming a conformal metal silicide region on all exposed surfaces of said conformal and rectangular-shaped epi semiconductor material; and forming a conductive material comprising a metal on said metal silicide region, all around said conformal and rectangular-shaped epi semiconductor material and above said layer of insulating material. ### Claim 14 (depends on 11) The method of claim 11, wherein, after performing said fin trimming process, said reduced-size fin portion is positioned adjacent a remaining portion of said initial fin structure positioned under said gate and wherein an upper surface of said reduced-size fin portion is at a level that is below a level of an upper surface of said remaining portion of said initial fin structure positioned under said gate. ### Claim 15 (depends on 14) The method of claim 14, wherein, after performing said fin trimming process, said reduced-size fin portion has a lateral width, in a gate-width direction of said device, at a location adjacent said upper surface of said reduced-size fin portion that is less than a lateral width, in said gate-width direction of said device, of said remaining portion of said initial fin structure positioned under said gate at a location adjacent an upper surface of said remaining portion of said initial fin structure positioned under said gate. ### Claim at position 16 -20. (canceled) ### Claim 21 A method of forming a FinFET device, comprising: forming a gate comprising a gate structure and a sidewall spacer positioned adjacent said gate structure around an initial fin structure and above a layer of insulating material, wherein said initial fin structure positioned in a source/drain region of said device comprises an exposed portion of said initial fin structure that is positioned above a level of an upper surface of said layer of insulating material and not covered by said gate, said exposed portion of said initial fin structure having a first size; performing a fin trimming process on said exposed portion of said initial fin structure after forming said sidewall spacer so as to produce a reduced-size fin portion positioned above said upper surface of said layer of insulating material in said source/drain region of said device, said reduced-size fin portion having a second size that is less than said first size; forming a conformal epi semiconductor material on an upper surface and sidewall surfaces of said reduced-size fin portion, wherein said sidewall surfaces extend in a direction parallel to an axial length of said reduced-size fin portion; and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around said conformal epi semiconductor material. ### Claim 22 (depends on 21) The method of claim 21, wherein forming said conformal epi semiconductor material comprises forming a conformal and rectangular-shaped epi semiconductor material on said reduced-size fin portion. ### Claim 23 (depends on 21) The method of claim 21, wherein, prior to performing said fin trimming process, said exposed portion of said initial fin structure in said source/drain region has a first height above said upper surface of said layer of insulating material and a first lateral width at a location that is approximately level with said upper surface of said layer of insulating material and wherein, after performing said fin trimming process, said reduced-size fin portion has a second height above said upper surface of said layer of insulating material and a second lateral width at a location adjacent an upper surface of said reduced-size fin portion, wherein said second height is less than said first height and said second width is less than said first width. ### Claim 24 (depends on 21) The method of claim 21, wherein forming said conductive source/drain contact structure comprises: forming a conformal metal silicide region on all exposed surfaces of said conformal epi semiconductor material; and forming a conductive material comprising a metal on said metal silicide region, all around said epi semiconductor material and above said layer of insulating material. ### Claim 25 (depends on 21) The method of claim 21, wherein, after performing said fin trimming process, said reduced-size fin portion is positioned adjacent a remaining portion of said initial fin structure positioned under said gate and wherein an upper surface of said reduced-size fin portion is at a level that is below a level of an upper surface of said remaining portion of said initial fin structure positioned under said gate, and said reduced-size fin portion has a lateral width, in a gate-width direction of said device, at a location adjacent said upper surface of said reduced-size fin portion that is less than a lateral width, in said gate-width direction of said device, of said remaining portion of said initial fin structure positioned under said gate at a location adjacent an upper surface of said remaining portion of said initial fin structure positioned under said gate.