# US 2018/0323264 A1 · Fabrication of wrap-around and conducting metal oxide contacts for igzo non-planar devices

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- Number: US 2018/0323264 A1
- Document ID: US20180323264A1
- Status: Published application
- Kind: A1
- Application number: 15/773,549
- Filed: 2015-12-23
- Published: 2018-11-08
- Earliest claimed: 2015-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Van H. LE; Rafael RIOS; Gilbert DEWEY; Jack T. KAVALIEROS; Marko RADOSAVLJEVIC
- Web page: https://patentgrep.com/patent/US20180323264A1

## CPC

- H10D 62/80: characterised by the materials
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/40: Crystalline structures
- H10D 62/402: {Amorphous materials}
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10P 14/20: of semiconductor materials
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/3454: {Amorphous}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a fmfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
an InGaZnO (IGZO) fin formed above the substrate
a source contact formed adjacent to more than one surface of the IGZO fin;
a drain contact formed adjacent to more than one surface of the IGZO fin; and
a gate electrode formed between the source contact and the drain contact, wherein the gate electrode is separated from the IGZO layer by a gate dielectric.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein source contact and the drain contact are adjacent to sidewall surfaces of the IGZO fin and a top surface of the IGZO fin.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the source contact and the drain contact directly contact the IGZO fin.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further comprising:
an interface layer positioned between the IGZO fin and the source and drain contacts.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the IGZO fin includes one or more alternating layers of an IGZO material and a sacrificial material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain contacts are separated from the gate electrode by at least the gate dielectric.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the source and drain contacts are separated from the gate electrode by at least the gate dielectric and a spacer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain contacts comprise a conductive oxide.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the conductive oxide is indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain contacts comprise a semiconducting material.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is a dielectric layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the dielectric layer is a layer in a back end of line (BEOL) stack of an integrated circuit chip.

### Claim 13

A method of forming a non-planar InGaZnO (IGZO) transistor, comprising:
forming a first layer over a substrate, wherein the first layer includes IGZO;
patterning the first layer to form a fin;
forming a dummy gate electrode over the fin;
forming a source contact and a drain contact on opposite sides of the dummy gate electrode, wherein the source and drain contact are adjacent to more than one surface of the fin;
removing the dummy gate electrode;
forming a gate dielectric layer on exposed portions of the IGZO; and
forming a gate electrode over the gate dielectric layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the source and drain region comprises:
forming a dielectric layer over the fin;
patterning the dielectric layer to form contact openings, wherein the contact openings have a width that is greater than a width of the fin; and
depositing a conductive material into the contact openings.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
depositing a conductive interface layer into the contact openings prior to depositing the conductive material, wherein the conductive interface layer conforms to the surfaces of the fin.

### Claim 16 (depends on 15)

The method of claim 15, wherein the conductive interface layer is deposited with an atomic layer deposition process.

### Claim 17 (depends on 13)

The method of claim 13, wherein the source and drain contacts comprise a conductive oxide.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the conductive oxide is indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

### Claim 19 (depends on 13)

The semiconductor device of claim 13, wherein the source and drain contacts comprise a semiconducting material.

### Claim 20 (depends on 13)

The method of claim 13, wherein the first layer includes a plurality of sacrificial material layers in an alternating pattern with a plurality of IGZO layers.

### Claim 21 (depends on 20)

The method of claim 20, further comprising:
removing a portion of the sacrificial material layers that is formed between the source region and the drain region prior to forming the gate dielectric layer.

### Claim 22

A semiconductor device, comprising:
a substrate;
a source contact formed over the substrate;
a drain contact formed over the substrate;
a gate electrode formed between the source contact and the drain contact, wherein the gate electrode is separated from drain contact and the source contact by at least a spacer layer; and
an InGaZnO (IGZO) nanowire formed through the gate electrode and contacting the source contact and the drain contact.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, wherein the IGZO nanowire passes through an opening in a residual spacer formed below the spacer layer.

### Claim 24 (depends on 23)

The semiconductor device of claim 23, wherein the residual spacer has a width that is less than a width of the spacer.

### Claim 25 (depends on 24)

The semiconductor device of claim 24, wherein the source contact and the drain contact completely encircle the surfaces of the IGZO nanowire.