# US 2018/0323263 A1 · Silicon carbide semiconductor substrate, method of manufacturing silicon carbide semiconductor substrate, semiconductor device and method of manufacturing semiconductor device

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- Number: US 2018/0323263 A1
- Document ID: US20180323263A1
- Status: Published application
- Kind: A1
- Application number: 16/019,531
- Filed: 2018-06-26
- Published: 2018-11-08
- Earliest claimed: 2016-07-29
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Takeshi TAWARA; Hidekazu TSUCHIDA; Tetsuya MIYAZAWA
- Web page: https://patentgrep.com/patent/US20180323263A1

## CPC

- H10D 62/8325: {Silicon carbide}
- C30B 25/183: {being provided with a buffer layer, e.g. a lattice matching layer}
- C30B 25/20: the substrate being of the same materials as the epitaxial layer
- C30B 29/36: Carbides
- H10D 62/60: Impurity distributions or concentrations
- H10P 14/20: of semiconductor materials
- H10P 14/3208: {Silicon carbide}
- H10P 14/3242: {Structure}
- H10P 30/22: using masks
- H10P 14/2904: {Silicon carbide}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3442: {N-type}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.

## Claims

### Claim 1

A silicon carbide semiconductor substrate comprising:
a silicon carbide substrate of a first conductivity type, the silicon carbide substrate having a central part and a peripheral part surrounding the central part, and being doped with a first impurity that determines the first conductivity type;
a buffer layer of the first conductivity type, the buffer layer being provided on a front surface of the central part of the silicon carbide substrate, and being doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity; and
an epitaxial layer of the first conductivity type, the epitaxial layer being provided on a front surface of the peripheral part of the silicon carbide substrate, and being doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.

### Claim 2 (depends on 1)

The silicon carbide semiconductor substrate according to claim 1, wherein
the buffer layer has a first side and a second side opposite to each other, the second side facing the silicon carbide substrate,
the epitaxial layer is a voltage blocking layer, and
the voltage blocking layer is further provided on the first side of the buffer layer.

### Claim 3 (depends on 1)

The silicon carbide semiconductor substrate according to claim 1, wherein
each of the buffer layer and the epitaxial layer has a first side and a second side opposite to each other, the second side of the buffer layer and the second side of the epitaxial layer both facing the silicon carbide substrate, and
the silicon carbide semiconductor substrate further includes a voltage blocking layer of the first conductivity type provided on the first side of the buffer layer and on the first side of the epitaxial layer, the voltage blocking layer being doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.

### Claim 4 (depends on 1)

The silicon carbide semiconductor substrate according to claim 1, wherein
a distance between an end of the silicon carbide substrate and an interface at which the central part connects the peripheral part is in a range from 0.1 mm to 30 mm.

### Claim 5

A method of manufacturing a silicon carbide semiconductor substrate, the method comprising:
preparing a silicon carbide substrate of a first conductivity type, the silicon carbide substrate having a central part and a peripheral part surrounding the central part, and being doped with a first impurity that determines the first conductivity type;
forming a buffer layer of the first conductivity type on a front surface of the central part of the silicon carbide substrate, the buffer layer being doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity, the buffer layer having a first side and a second side opposite to each other, the second side facing the silicon carbide substrate; and
forming a voltage blocking layer of the first conductivity type on a front surface of the peripheral part of the silicon carbide substrate and on the first side of the buffer layer, the voltage blocking layer being doped with the first impurity, a concentration of which is lower than the concentration of the first impurity in the buffer layer.

### Claim 6 (depends on 5)

The method according to claim 5, wherein
the buffer layer is formed by epitaxial growth, after a cover that covers the peripheral part is placed on a front surface of the silicon carbide substrate.

### Claim 7 (depends on 5)

The method according to claim 5, wherein
a distance between an end of the silicon carbide substrate and an interface at which the central part connects the peripheral part is in a range from 0.1 mm to 30 mm.

### Claim 8

A method of manufacturing a silicon carbide semiconductor substrate, the method comprising:
preparing a silicon carbide substrate of a first conductivity type, the silicon carbide substrate having a central part and a peripheral part surrounding the central part, and being doped with a first impurity that determines the first conductivity type;
forming an epitaxial layer of the first conductivity type on a front surface of the silicon carbide substrate, the epitaxial layer being doped with the first impurity, of which a concentration is lower than a concentration of the first impurity in the silicon carbide substrate, the epitaxial layer having a first side and a second side opposite to each other, the second side facing the silicon carbide substrate;
forming a buffer layer of the first conductivity type in a region of the epitaxial layer corresponding to the central part of the silicon carbide substrate, the buffer layer being doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity, the buffer layer having a first side and a second side opposite to each other, the second side facing the silicon carbide substrate; and
forming a voltage blocking layer of the first conductivity type on the first side of the epitaxial layer and the first side of the buffer layer, the voltage blocking layer being doped with the first impurity, a concentration of which is lower than the concentration of the first impurity in the buffer layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein
the buffer layer is formed by ion implantation, after a mask having an opening corresponding to the region is formed on the first side of the epitaxial layer.

### Claim 10 (depends on 8)

The method according to claim 8, wherein
a distance between an end of the silicon carbide substrate and an interface at which the central part connects the peripheral part is in a range from 0.1 mm to 30 mm.