# US 2018/0323260 A1 · Dual threshold voltage (vt) channel devices and their methods of fabrication

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- Number: US 2018/0323260 A1
- Document ID: US20180323260A1
- Status: Published application
- Kind: A1
- Application number: 15/773,536
- Filed: 2015-12-23
- Published: 2018-11-08
- Earliest claimed: 2015-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Hsu-Yu CHANG; Neville L. DIAS; Walid M. HAFEZ; Chia-Hong JAN; Roman W. OLAC-VAW; Chen-Guan LEE
- Web page: https://patentgrep.com/patent/US20180323260A1

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

## Claims

### Claim 1

A semiconductor device comprising:
a gate stack disposed on a substrate, the substrate having a first lattice constant;
a source region and a drain region formed on opposite sides of the gate electrode; and
a channel region disposed beneath the gate stack and between the source region and the drain region, wherein the source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth, the first recess deeper than the second recess, and wherein a semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein the first depth is at least 20% greater than the second depth.

### Claim 3 (depends on 2)

The semiconductor device of claim 2 wherein the first depth is between 20-70% greater than the second depth.

### Claim 4 (depends on 1)

The semiconductor device of claim 1 further comprising a source side structure disposed over the substrate wherein the source side structure is spaced apart from the gate stack by a first distance, and a drain side structure disposed on the substrate, wherein the drain side structure is spaced apart from the stack by a second distance, wherein the first distance is greater than the second distance.

### Claim 5 (depends on 1)

The semiconductor device of claim 1 wherein the semiconductor substrate is a silicon monocrystalline substrate and wherein said semiconductor material is silicon germanium.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the channel region comprises a first semiconductor portion having a first band gap adjacent to the source region and a second semiconductor portion having a second band gap adjacent to the drain region, wherein the second band gap is smaller than the first band gap.

### Claim 7 (depends on 1)

The semiconductor device of claim 1 wherein the channel region has a channel length and wherein the second portion has a length between 20-50% of the channel length.

### Claim 8

A semiconductor device comprising:
a gate stack disposed on a substrate having a first lattice constant;
a source region and a drain region disposed on opposite sides of the gate stack; and
a channel region disposed beneath the gate stack and between the source region and the drain region, wherein the channel region comprises a first semiconductor portion having a first band gap adjacent to the source region and a second semiconductor portion having a second band gap adjacent to the drain region, the second band gap smaller than the first band gap.

### Claim 9 (depends on 8)

The semiconductor device of claim 8 wherein the channel region has a channel length and wherein the second portion has a length which is between 20-50% of the channel length.

### Claim 10 (depends on 8)

The semiconductor device of claim 8 wherein the source region is formed in a first recess and wherein the drain region is formed in a second recess, and wherein the first recess and the second recess have a same depth.

### Claim 11 (depends on 8)

The semiconductor device of claim 8 wherein the second semiconductor portion extends to at least an inversion depth of the semiconductor device beneath the gate stack.

### Claim 12 (depends on 8)

The semiconductor device of claim 8 wherein the second semiconductor portion extends a depth between 20-60 nm beneath the gate stack.

### Claim 13 (depends on 8)

The semiconductor device of claim 8 wherein the semiconductor substrate is monocrystalline silicon substrate and wherein the first semiconductor portion is formed from the monocrystalline silicon substrate and wherein the second semiconductor portion is silicon germanium.

### Claim 14 (depends on 13)

The semiconductor device of claim 13 wherein the silicon germanium comprises between 10-30 atomic percent germanium.

### Claim 15 (depends on 13)

The semiconductor device of claim 13 wherein the silicon germanium is graded to have a higher concentration of germanium proximate to the drain region and a lower concentration of germanium proximate to the first semiconductor portion of the channel region.

### Claim 16

A method of forming semiconductor device comprising:
forming a first gate stack on a semiconductor substrate having a first lattice constant;
forming a first recess on a source side of the gate stack to a first depth and forming a second recess on the drain side of the gate stack to a second depth, wherein the first depth is greater than the second depth; and
forming a semiconductor material in the first recess to form a source region and forming the semiconductor material in the second recess to form a drain region, wherein semiconductor material has a second lattice constant, wherein the second lattice constant is different than the first lattice constant.

### Claim 17 (depends on 16)

The method of claim 16 further comprising:
forming a second gate stack on the source side of the first gate stack and forming a third gate stack on the drain side of the first gate stack, wherein the second gate stack is separated from the first gate stack by a first distance and wherein the third gate stack is separated from the first gate stack by a second distance, wherein the first distance is greater than the second distance; and
wherein forming the first recess and forming the second recess comprise simultaneously etching the semiconductor substrate between the first and second gate stacks and the semiconductor substrate between the first and third gate stacks.

### Claim 18 (depends on 16)

The method of claim 16 further comprising placing atoms into the substrate beneath the gate stack adjacent to the drain side of the device.

### Claim 19 (depends on 18)

The method of claim 18 wherein the atoms are placed in the substrate prior to forming the first recess and the second recess.

### Claim 20 (depends on 16)

The method of claim 16 wherein the atoms reduce the band gap of the semiconductor substrate beneath the gate stack.

### Claim 21

A method of forming a semiconductor device comprising:
forming a gate stack on a semiconductor substrate, the semiconductor substrate having a first bandgap;
implanting atoms at an angle into the substrate on a drain side of the gate stack such that the atoms are located beneath the gate stack on the drain side but not beneath the gate stack on a source side; and
forming a source region on the source side of the gate stack and a drain region on the drain side of the gate stack.

### Claim 22 (depends on 21)

The method of claim 21 wherein forming a source region and a drain region comprise forming a first recess in the substrate on the source side of the gate stack and forming a second recess on the drain side of the gate stack; and
depositing a semiconductor material into the first recess and the second recess.

### Claim 23 (depends on 22)

The method of claim 22 wherein the semiconductor material has a lattice constant which is different from than the lattice constant of the substrate.

### Claim 24 (depends on 21)

The method of claim 21 wherein the atoms are implanted at an implant angle of between 30°-60° from a direction normal to the substrate.

### Claim 25 (depends on 21)

The method of claim 21 wherein the substrate is a monocrystalline silicon substrate and the atoms are germanium atoms.