# US 2018/0323259 A1 · Semiconductor device and method of fabricating the same

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- Number: US 2018/0323259 A1
- Document ID: US20180323259A1
- Status: Published application
- Kind: A1
- Application number: 15/588,804
- Filed: 2017-05-08
- Published: 2018-11-08
- Earliest claimed: 2017-05-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Martin Christopher HOLLAND; Mark VAN DAL; Georgios VELLIANITIS; Blandine DURIEZ; Gerben DOORNBOS
- Web page: https://patentgrep.com/patent/US20180323259A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01: Manufacture or treatment
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/514: {characterised by the insulating layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.

## Claims

### Claim 1

A semiconductor device comprising:
a multi-layer stack comprising a first nanowire in a first layer of the multi-layer stack and a second nanowire in a second layer of the multi-layer stack, wherein a first portion of the first nanowire and a first portion of the second nanowire are positioned in an overlying relationship;
an epitaxial layer wrapping around the first portion of the first nanowire and the first portion of the second nanowire; and
a gate disposed over a second portion of the first nanowire and a second portion of the second nanowire, which are positioned in an overlying relationship.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the epitaxial layer is interposed in between the first nanowire and the second nanowire.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the epitaxial layer has a zig-zag contour.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the epitaxial layer includes Ge, Si, SiGe or a combination thereof.

### Claim 5

(canceled)

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a surface of the epitaxial layer is a <111> plane.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate comprises a high-k dielectric layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gate comprises a work function metal layer.

### Claim 9

A semiconductor device comprising:
a plurality of nanowires, wherein first portions of the nanowires are positioned in an overlying relationship and are doped to form source and drain regions;
an epitaxial layer having at least a portion interposed in between the first portions of the nanowires; and
a gate disposed over second portions of the nanowires.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the epitaxial layer has a zig-zag contour.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the epitaxial layer includes Ge, Si, SiGe or a combination thereof.

### Claim 12

(canceled)

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein a surface of the epitaxial layer is a <111> plane.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the gate comprise a high-k dielectric layer.

### Claim at position 15

-20. (canceled)

### Claim 21

A semiconductor device comprising:
a multi-layer stack comprising a nanowire;
an epitaxial layer wrapping around a first portion of the nanowire in a diamond shape, wherein the nanowire and the epitaxial layer form an interface extending along a lengthwise direction of the nanowire; and
a gate disposed over a second portion of the nanowire.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the epitaxial layer has a zig-zag contour.

### Claim 23 (depends on 21)

The semiconductor device of claim 21, wherein the epitaxial layer comprises silicon germanium.

### Claim at position 19

24-25. (canceled)

### Claim 26 (depends on 21)

The semiconductor device of claim 21, wherein the gate comprises a high-k dielectric layer.

### Claim 27 (depends on 1)

The semiconductor device of claim 1, wherein the epitaxial layer is in contact with at least a bottom surface of the first portion of the first nanowire.

### Claim 28 (depends on 9)

The semiconductor device of claim 9, wherein the epitaxial layer encircles at least one of the first portions of the nanowires.

### Claim 29 (depends on 21)

The semiconductor device of claim 21, wherein the gate is separated from the epitaxial layer.

### Claim 30 (depends on 21)

The semiconductor device of claim 21, wherein the interface of the nanowire and the epitaxial layer covers at least a bottom surface of the nanowire.