# US 2018/0323256 A1 · Fin-type field effect transistor and method of forming the same

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- Number: US 2018/0323256 A1
- Document ID: US20180323256A1
- Status: Published application
- Kind: A1
- Application number: 16/040,319
- Filed: 2018-07-19
- Published: 2018-11-08
- Earliest claimed: 2015-10-02
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Huai-Tzu Chiang; Sheng-Hao Lin; Hao-Ming Lee; Yu-Ru Yang; Shih-Hsien Huang; Chien-Hung Chen; Chun-Yuan Wu; Cheng-Tzung Tsai
- Web page: https://patentgrep.com/patent/US20180323256A1

## CPC

- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

## Claims

### Claim 1

A method of forming a FinFET, comprising:
providing a substrate, wherein the substrate has an insulating layer formed thereon, the insulating layer has at least one trench formed therein, and the at least one trench extends to a portion of the substrate;
sequentially forming a seed layer, a stress relaxation layer and a channel layer in the at least one trench;
removing a portion of the insulating layer, so as to expose a portion of the channel layer; and
forming at least one gate across the channel layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming an anti-punch through layer between the stress relaxation layer and the channel layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein a germanium concentration of the channel layer is substantially equal to a germanium concentration of the anti-punch through layer, the germanium concentration of the anti-punch through layer is greater than a germanium concentration of the stress relaxation layer, and the germanium concentration of the stress relaxation layer is greater than a germanium concentration of the seed layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the stress relaxation layer has a graded stress distribution, and a germanium concentration of the stress relaxation layer is gradually increased from the seed layer towards the anti-punch through layer.

### Claim 5 (depends on 2)

The method of claim 2, wherein a method of forming each of the seed layer, the stress relaxation layer, the anti-punch through layer and the channel layer comprises performing an epitaxial growth process.

### Claim 6 (depends on 2)

The method of claim 2, wherein a dopant concentration of the anti-punch through layer is greater than a dopant concentration of the stress relaxation layer or the channel layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein a dopant of the anti-punch through layer comprises arsenic, phosphorus or boron.

### Claim 8 (depends on 2)

The method of claim 2, wherein a surface of the remaining insulating layer is higher than an interface between the anti-punch through layer and the channel layer after the step of removing the portion of the insulating layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein a method of forming the at least one trench comprises:
providing the substrate with at least one dummy fin, wherein the insulating layer surrounds the at least one dummy fin; and
performing an etching process, so as to remove the at least one dummy fin and a portion of the substrate.

### Claim 10 (depends on 1)

The method of claim 1, wherein a germanium concentration of the channel layer ranges from about 20% to 100%.

### Claim 11 (depends on 1)

The method of claim 1, wherein the substrate and the seed layer have substantially the same lattice constant, and the anti-punch through layer and the channel layer have substantially the same lattice constant.

### Claim 12 (depends on 1)

The method of claim 1, wherein the stress relaxation layer comprises germanium, the channel layer comprises a semiconductor material, the stress relaxation layer and the seed layer comprise different materials, and the seed layer has a tapered v-shaped tip at a bottom end thereof.