# US 2018/0323255 A1 · On-chip mim capacitor

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- Number: US 2018/0323255 A1
- Document ID: US20180323255A1
- Status: Published application
- Kind: A1
- Application number: 16/019,606
- Filed: 2018-06-27
- Published: 2018-11-08
- Earliest claimed: 2016-09-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Peng Xu
- Web page: https://patentgrep.com/patent/US20180323255A1

## CPC

- H10D 1/692: {Electrodes}
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/714: {having horizontal extensions}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D 84/853: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- H10P 50/264: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.

## Claims

### Claim 1

A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:
a first capacitor electrode formed between gate structure regions in a capacitor region and formed from contact metal for contacts to source and drain (S/D) regions in a CMOS region;
an insulator formed in contact with the first electrode in the gate structure regions in the capacitor region; and
a second electrode formed in a plurality of loops in contact with the insulator within the gate structure regions in the capacitor region to form the on-chip capacitor.

### Claim 2 (depends on 1)

The device as recited in claim 1, wherein the CMOS region includes fin field effect transistors.

### Claim 3 (depends on 1)

The device as recited in claim 1, wherein the insulator includes a dielectric spacer and a gate dielectric layer, wherein the gate dielectric layer is employed with gate structures in the CMOS region.

### Claim 4 (depends on 1)

The device as recited in claim 1, wherein the first and second electrodes include different materials.

### Claim 5 (depends on 1)

The device as recited in claim 1, further including a gate cut trench structure including cuts in the gate structures in the CMOS region at longitudinal end portions and midspan.

### Claim 6 (depends on 1)

The device as recited in claim 1, wherein the insulator includes sidewall spacers for the gate structures in the CMOS region and the capacitor region.

### Claim 7 (depends on 1)

The device as recited in claim 1, wherein the device includes a system-on-chip (SOC).

### Claim 8 (depends on 1)

The device as recited in claim 1, wherein the loop structures connect to a common conductive region formed in a gate cut trench in the capacitor region.

### Claim 9

A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:
a first capacitor electrode formed between gate structure regions in a capacitor region;
a gate cut trench structure formed in the capacitor region and filled with a conductive material;
an insulator formed in contact with the first electrode in the gate structure regions in the capacitor region; and
a second electrode formed in contact with the insulator spacer within the gate structure regions in the capacitor region to form the on-chip capacitor.

### Claim 10 (depends on 9)

The device as recited in claim 9, wherein the insulator includes a dielectric spacer and a gate dielectric layer, wherein the gate dielectric layer is employed with gate structures in the CMOS region.

### Claim 11 (depends on 9)

The device as recited in claim 9, wherein the first and second electrodes include different materials.

### Claim 12 (depends on 9)

The device as recited in claim 9, wherein the gate cut trench structure includes cuts in the gate structures in the CMOS region at longitudinal end portions and midspan.

### Claim 13 (depends on 9)

The device as recited in claim 9, wherein the insulator includes sidewall spacers for the gate structures in the CMOS region and the capacitor region.

### Claim 14 (depends on 9)

The device as recited in claim 9, wherein the device includes a system-on-chip (SOC).

### Claim 15 (depends on 9)

The device as recited in claim 9, wherein the second electrode includes a plurality of loop structures in the capacitor region.

### Claim 16 (depends on 15)

The device as recited in claim 15, wherein the loop structures connect to a common conductive region formed in a gate cut trench in the capacitor region.

### Claim 17

A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:
a gate structure disposed in a capacitor region and in a CMOS region;
insulating spacers disposed on sides of the gate structure in the capacitor region and the CMOS region;
a first electrode disposed between the insulating spacer of the gate structure in the capacitor region; and
a second electrode in contact with the insulating spacers such that the insulating spacers are disposed between the first electrode and the second electrode.

### Claim 18 (depends on 17)

The device as recited in claim 17, further including a gate cut trench structure including cuts in a gate structure in the CMOS region at longitudinal end portions and midspan.

### Claim 19 (depends on 17)

The device as recited in claim 17, wherein the first electrode forms a plurality of loops in the capacitor region.

### Claim 20 (depends on 17)

The device as recited in claim 17, wherein the insulating spacers include a dielectric spacer and a gate dielectric layer, wherein the gate dielectric layer is employed with gate structures in the CMOS region.