# US 2018/0323238 A1 · Resistive memory cell structures and methods

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- Number: US 2018/0323238 A1
- Document ID: US20180323238A1
- Status: Published application
- Kind: A1
- Application number: 16/022,945
- Filed: 2018-06-29
- Published: 2018-11-08
- Earliest claimed: 2012-01-18
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Fabio Pellizzer; Ferdinando Bedeschi
- Web page: https://patentgrep.com/patent/US20180323238A1

## CPC

- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/041: {Modification of switching materials after formation, e.g. doping (shaping H10N70/061)}
- H10N 70/043: {by implantation}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8613: {Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

## Claims

### Claim at position 1

-20. (canceled)

### Claim 21

A method of forming an array of resistive memory cells, the method comprising:
forming a first number of resistive memory cells in a first region of the array and a second number of resistive memory cells in a second region of the array; and
modifying an electrothermal property of a resistance variable material in at least one of the first region of the array and the second region of the array.

### Claim 22 (depends on 21)

The method of claim 21, wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second regions includes at least one of performing a first ion implantation process on at least a portion of the first region and performing a second ion implantation on at least a portion of the second region.

### Claim 23 (depends on 22)

The method of claim 22, wherein performing the at least one of the first implantation process and the second ion implantation process includes implanting ions through a cap material formed on the resistance variable material.

### Claim 24 (depends on 21)

The method of claim 21, wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second regions includes:
forming a first reactant material on the resistance variable material in the first region; and
forming a second reactant material on the resistance variable material in the second region.

### Claim 25 (depends on 21)

The method of claim 21, wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second regions includes thermal activation to modify the electrothermal properties of the resistance variable material in the first and second regions of the array.

### Claim 26 (depends on 21)

The method of claim 21, wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second regions includes:
forming a reactant material of a first thickness on the resistance variable material in the first region; and
forming the reactant material of a different thickness on the resistance variable material in the second region.

### Claim 27 (depends on 24)

The method of claim 24, wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second regions includes:
removing a portion of the first reactant material;
forming the second reactant material where the portion of the first reactant material was removed and on the resistance variable material in the second region;
forming a cap material on the second reactant material; and
forming separate cell stacks corresponding to the respective first and second resistive memory cells.

### Claim 28 (depends on 21)

The method of claim 21, wherein modifying the electrothermal property of the resistance variable material in the at least one of the first and second regions includes:
performing a first ion implantation process using an ion of a first concentration on at least a portion of the first region; and
performing a second ion implantation using an ion of a second concentration on at least a portion of the second region,
wherein the first ion concentration is different than the second ion concentration.

### Claim 29

A method of forming an array of resistive memory cells, the method comprising:
forming a first conductive material in a first region and a second region of the array;
forming a resistance variable material on the first conductive material;
forming a second conductive material on the resistance variable material;
removing a portion of the second conductive material from the second region of the array;
forming a third conductive material on the second conductive material in the first region and on the resistance variable material in the second region of the array;
forming a fourth conductive material on the third conductive material; and
defining individual resistive memory cells by removing portions of the first and second resistance variable materials and portions of the first, second, third, and fourth conductive materials.

### Claim 30 (depends on 29)

The method of claim 29, further comprising the second conductive material reacting with the resistance variable material in the first region and the third conductive material reacting with the resistance variable material in the second region to modify an electrothermal property of the resistance variable material.

### Claim 31 (depends on 30)

The method of claim 30, wherein the reactions are thermally activated.

### Claim 32 (depends on 29)

The method of claim 29, wherein the second conductive material and the third conductive material are the same conductive material.

### Claim 33 (depends on 29)

The method of claim 29, wherein forming the array includes:
forming the first resistance variable material on the first conductive material formed on the first and second region;
forming a first cap material on the first resistance variable material;
removing the first resistance variable material and the first cap material from the second region;
forming the second resistance variable material on the first cap material of the first region and on the conductive material of the second region;
forming a second cap material on the second resistance variable material;
removing the second resistance variable material and the second cap material from the first region; and
forming separate cell stacks corresponding to the respective first and second number of resistive memory cells.

### Claim 34 (depends on 29)

The method of claim 29, wherein forming the array includes:
forming a first via in a dielectric formed on the first region and the second region of the array;
forming the first resistance variable material on the first and the second region of the array, the first resistance variable material filling the first via;
forming a first cap material on the first resistance variable material;
removing a portion of the first resistance variable material and a portion of the first cap material from the second region of the array;
forming a second via in the dielectric formed on the second region of the array;
forming the second resistance variable material on the first and second region of the array, the second resistance variable material filling the second via;
forming a second cap material on the second resistance variable material;
removing the second resistance variable material and the second cap material from the first region of the array;
performing an etch process such that the first resistance variable material is confined to the first via and the second resistance variable material is confined to the second via; and
forming a metal material on the first resistance variable material formed in the first via and on the second resistance variable material formed in the second via.

### Claim 35 (depends on 29)

The method of claim 29, wherein the first and second cap materials serve as bit lines for the respective first and second number of resistive memory cells.

### Claim 36 (depends on 29)

The method of claim 29, further comprising forming the first conductive material on a number of conductive plugs coupled to respective select devices corresponding to the first number of resistive memory cells and to the second number of resistive memory cells.

### Claim 37

A method of forming an array of resistive memory cells, the method comprising:
forming a first resistance variable material on a first conductive material formed in a first and a second region of the array;
forming a first cap material on the first resistance variable material;
removing the first resistance variable material and the first cap material from the second region;
forming the second resistance variable material on the first cap material of the first region and on the conductive material of the second region;
forming a second cap material on the second resistance variable material;
removing the second resistance variable material and the second cap material from the first region; and
forming separate cell stacks corresponding to the respective first and second number of resistive memory cells.

### Claim 38 (depends on 37)

The method of claim 37, wherein forming the array comprises:
forming a first number of resistive memory cells in the first region of the array, the first number of cells comprising the first resistance variable material; and
forming a second number of resistive memory cells in the second region of the array, the second number of cells comprising the second resistance variable material that is different than the first resistance variable material.

### Claim 39 (depends on 38)

The method of claim 38, wherein the first and second cap materials serve as bit lines for the respective first and second number of resistive memory cells.

### Claim 40 (depends on 38)

The method of claim 38, wherein the first and second resistance variable materials include different chalcogenide alloys.