# US 2018/0323213 A1 · Semiconductor device and method for manufacturing same

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- Number: US 2018/0323213 A1
- Document ID: US20180323213A1
- Status: Published application
- Kind: A1
- Application number: 16/040,292
- Filed: 2018-07-19
- Published: 2018-11-08
- Earliest claimed: 2017-02-28
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Shinya ARAI
- Web page: https://patentgrep.com/patent/US20180323213A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10D 62/834: further characterised by the dopants
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a source layer including a semiconductor layer including an impurity;
a stacked body provided above the source layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed;
a gate layer provided between the source layer and the stacked body, the gate layer being thicker than a thickness of one layer of the electrode layers;
a semiconductor body extending in a stacking direction of the stacked body through the stacked body and the gate layer, the semiconductor body further extending in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer, the semiconductor body not contacting the electrode layers and the gate layer; and
a charge storage portion provided between the semiconductor body and one of the electrode layers.

### Claim 2 (depends on 1)

The device according to claim 1, wherein a distance between the side wall portion and a portion of the semiconductor body opposing the gate layer is less than a thickness of the gate layer.

### Claim 3 (depends on 1)

The device according to claim 1, wherein an impurity concentration of the side wall portion of the semiconductor body is higher than an impurity concentration of a portion of the semiconductor body opposing the stacked body.

### Claim 4 (depends on 1)

The device according to claim 1, wherein an impurity concentration of a portion of the semiconductor body opposing the gate layer is higher than an impurity concentration of a portion of the semiconductor body opposing the stacked body.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the electrode layers include:
a drain-side selection gate thinner than the gate layer, the drain-side selection gate being at least one layer;
a source-side selection gate provided between the drain-side selection gate and the gate layer, the source-side selection gate being at least one layer and being thinner than the gate layer; and
a plurality of cell gates opposing the charge storage portion and being provided between the drain-side selection gate and the source-side selection gate, the plurality of cell gates each being thinner than the gate layer.

### Claim 6 (depends on 1)

The device according to claim 1, wherein the gate layer is a silicon layer including phosphorus.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the semiconductor layer is a silicon layer including phosphorus.

### Claim 8 (depends on 1)

The device according to claim 1, wherein
the source layer further includes a layer including a metal, and
the semiconductor layer is provided between the gate layer and the layer including the metal.

### Claim 9 (depends on 1)

The device according to claim 1, wherein the charge storage portion is continuous in the stacking direction between the stacked body and the semiconductor body.

### Claim 10 (depends on 9)

The device according to claim 9, wherein an insulating film is provided between the gate layer and the semiconductor body, the insulating film including the same type of film as the charge storage portion.

### Claim 11 (depends on 9)

The device according to claim 9, wherein an insulating film is provided under a bottom surface of the semiconductor body, the insulating film including the same type of film as the charge storage portion.

### Claim 12 (depends on 1)

The device according to claim 1, wherein a potential causing GIDL (gate induced drain leakage) to occur in a portion of the semiconductor body opposing the gate layer is applied to the gate layer in an erase operation.

### Claim 13 (depends on 1)

The device according to claim 1, wherein
the semiconductor layer includes:
a first semiconductor layer;
a second semiconductor layer provided between the first semiconductor layer and the gate layer; and
a third semiconductor layer provided along an upper surface of the first semiconductor layer, a lower surface of the second semiconductor layer, and the side wall portion of the semiconductor body, and
an air gap is formed between the third semiconductor layer provided on the upper surface of the first semiconductor layer and the third semiconductor layer provided on the lower surface of the second semiconductor layer.

### Claim 14

A method for manufacturing a semiconductor device, comprising:
forming a sacrificial layer above a first semiconductor layer;
forming a second semiconductor layer above the sacrificial layer;
forming an insulating layer above the second semiconductor layer;
forming a gate layer above the insulating layer, the gate layer being thicker than the second semiconductor layer;
forming a stacked body above the gate layer, the stacked body including a plurality of first layers and a plurality of second layers, the first layers and the second layers including a first layer and a second layer stacked alternately;
forming a semiconductor body inside a hole, the hole piercing the stacked body, the gate layer, the insulating layer, the second semiconductor layer, and the sacrificial layer;
forming a slit after the forming of the semiconductor body, the slit piercing the stacked body, the gate layer, the insulating layer, and the second semiconductor layer and reaching the sacrificial layer;
forming an air gap between the first semiconductor layer and the second semiconductor layer by removing the sacrificial layer through the slit;
exposing a portion of the semiconductor body in the air gap; and
forming a third semiconductor layer inside the air gap, the third semiconductor layer including an impurity and contacting the portion of the semiconductor body.

### Claim 15 (depends on 14)

The method according to claim 14, wherein
the first semiconductor layer, the second semiconductor layer, the sacrificial layer, and the gate layer are silicon layers,
a protective film is formed between the first semiconductor layer and the sacrificial layer, and between the sacrificial layer and the second semiconductor layer, the protective film being of a material different from the silicon layers, and
the sacrificial layer is removed in a state in which a side surface of the slit is covered with a liner film of a material different from the silicon layers.

### Claim 16 (depends on 14)

The method according to claim 14, wherein
the first semiconductor layer, the second semiconductor layer, and the gate layer are silicon layers, and
the sacrificial layer is a silicon nitride layer.

### Claim 17 (depends on 14)

The method according to claim 14, wherein
an insulating film is formed on a side surface of the hole prior to the forming of the semiconductor body, and
the portion of the semiconductor body is exposed in the air gap by removing a portion of the insulating film exposed in the air gap after the removing of the sacrificial layer.

### Claim 18 (depends on 14)

The method according to claim 14, wherein thermal diffusion of the impurity into the portion of the semiconductor body and into a portion of the semiconductor body opposing the insulating layer is performed in the forming of the third semiconductor layer or after the forming of the third semiconductor layer.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the impurity is diffused also into a portion of the semiconductor body opposing the gate layer.

### Claim 20 (depends on 14)

The method according to claim 14, further comprising replacing the first layers with electrode layers through the slit.

### Claim 21 (depends on 1)

The device according to claim 1, further comprising a substrate, the source layer being provided between the substrate and the gate layer, the semiconductor layer of the source layer contacting the substrate.

### Claim 22 (depends on 21)

The device according to claim 21, wherein
the substrate includes
an n-type semiconductor region contacting the semiconductor layer of the source layer, and
a p-type semiconductor region, the n-type semiconductor region and the p-type semiconductor region forming a p-n junction.

### Claim 23 (depends on 21)

The device according to claim 21, wherein the semiconductor body pierces the source layer, and a lower end portion of the semiconductor body reaches the substrate.

### Claim 24 (depends on 21)

The device according to claim 21, further comprising
a plug provided between the source layer and a peripheral portion of the gate layer, the plug connecting the source layer and the peripheral portion of the gate layer, and
a separation portion separating the gate layer into the peripheral portion and a cell portion.