# US 2018/0323211 A1 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0323211 A1 - Document ID: US20180323211A1 - Status: Published application - Kind: A1 - Application number: 16/031,588 - Filed: 2018-07-10 - Published: 2018-11-08 - Earliest claimed: 2016-05-04 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: In Su PARK; Ki Hong LEE; Hye Jeong CHEON - Web page: https://patentgrep.com/patent/US20180323211A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 64/037: {comprising charge-trapping insulators} - H10P 14/6546: {to change the surface groups of the insulating materials} - H10P 14/6516: {of treatments performed after formation of the materials} - H10P 14/69215: {the material being a silicon oxide, e.g. SiO2} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer. ## Claims ### Claim 1 A semiconductor device comprising: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein each of the buffer patterns is solely formed of the densified area and contacts the data storage layer. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the conductive area has a first edge, wherein the first edge is defined by the buffer patterns and the data storage layer, and wherein the first edge of the conductive area has a right angle. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the interlayer insulating layers have sidewalls that contact the buffer patterns, respectively, and wherein the densified area further extends from each of the buffer patterns into each of sidewalls of the interlayer insulating layers. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the conductive area has a first edge, wherein the first edge is defined by the densified area of each of the buffer patterns, the densified area extending in each of the interlayer insulating layers, and the data storage layer, and wherein the first edge of the conductive area is right-angled or rounded. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the densified area is formed along a first sidewall of each of the buffer patterns, wherein the first sidewall is adjacent to the data storage layer, wherein each of the buffer patterns further includes a non-densified area, and wherein the non-densified area is disposed between each of the interlayer insulating layers and the densified area. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the conductive area has a first edge, wherein the first edge is defined by the densified area of each of the buffer patterns, the non-densified area of each of the buffer patterns, and the data storage layer, and wherein the first edge of the conductive area is rounded. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the data storage layer comprises: first areas disposed between the buffer patterns and the channel layer; and a second area disposed between the blocking insulating pattern and the channel layer, the second area being thinner than the first areas. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the data storage layer comprises: a first sidewall facing the channel layer and having a planar structure; and a second sidewall facing the interlayer insulating layers and the conductive pattern and having an uneven surface structure. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein a densification degree of the densified area is gradually increased from each of the interlayer insulating layers toward the channel layer. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the densification degree is in reverse proportion to a number of dangling bonds included in each of the buffer patterns. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein a density of the densified area is a higher than a density of each of the interlayer insulating layers. ### Claim 13 A semiconductor device comprising: interlayer insulating layers and conductive patterns alternately stacked on each other; a channel layer passing through the interlayer insulating layers and the conductive patterns; and a buffer pattern disposed between the channel layer and each of the interlayer insulating layers, wherein the buffer pattern includes a densified area having a higher density than each of densities of the interlayer insulating layers. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein a number of dangling bonds included in the densified area is gradually decreased from the interlayer insulating layers toward the channel layer. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein a densification degree of the densified area is gradually increased from the interlayer insulating layers toward the channel layer. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, further comprising a data storage layer disposed between the channel layer and each of the conductive patterns. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the data storage layer extends between the buffer pattern and each of the interlayer insulating layers, and the densified area extends from a first sidewall of the buffer pattern to a second sidewall of the buffer pattern, and wherein the first sidewall is toward the data storage layer and the second sidewall is toward the interlayer insulating layers. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the densified area extends into each of the interlayer insulating layers. ### Claim 19 (depends on 13) The semiconductor device according to claim 13, wherein the buffer pattern further includes a non-densified area defined between the densified area and each of the interlayer insulating layers.