# US 2018/0323209 A1 · Three-dimensional semiconductor devices

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- Number: US 2018/0323209 A1
- Document ID: US20180323209A1
- Status: Published application
- Kind: A1
- Application number: 16/021,295
- Filed: 2018-06-28
- Published: 2018-11-08
- Earliest claimed: 2010-11-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: CHANGHYUN LEE; CHANJIN PARK; BYOUNGKEUN SON; SUNG-IL CHANG
- Web page: https://patentgrep.com/patent/US20180323209A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

## Claims

### Claim at position 1

-42. (canceled)

### Claim 43

A three-dimensional semiconductor device comprising:
a semiconductor substrate, an underlying layer on the semiconductor substrate, and a first structure on the underlying layer;
an opening penetrating at least the first structure;
an insulating layer on an inner wall of the opening;
a recessed hole disposed at a lower end of the opening and exposing a portion of the semiconductor substrate;
an insulating spacer in the opening; and
a semiconductor pattern covering the insulating spacer in the opening and being in direct contact with an inner wall of the recessed hole,
wherein a bottom surface of the insulating spacer is positioned at a vertical level equivalent to or higher than an uppermost surface of the semiconductor substrate.

### Claim 44 (depends on 43)

The device as claimed in claim 43, wherein the semiconductor pattern is directly connected to the semiconductor substrate.

### Claim 45 (depends on 44)

The device as claimed in claim 44, wherein the semiconductor substrate includes:
a doped region apart from the semiconductor pattern, the doped region having a different conductivity type from the semiconductor pattern; and
a connection region directly connected to the semiconductor pattern, the connection region having the same conductivity type as the semiconductor pattern.

### Claim 46 (depends on 43)

The device as claimed in claim 43, further comprising a selection transistor interposed between the semiconductor substrate and the first structure.

### Claim 47 (depends on 43)

The device as claimed in claim 43, wherein the semiconductor pattern is in direct contact with the bottom surface of the insulating spacer.

### Claim 48 (depends on 43)

The device as claimed in claim 43, wherein a distance between the bottom surface of the insulating spacer and an uppermost surface of the semiconductor substrate is less than a thickness of one of the conductive patterns.

### Claim 49 (depends on 43)

The device as claimed in claim 43, wherein the underlying layer is formed of aluminum oxide.

### Claim 50 (depends on 43)

The device as claimed in claim 43, wherein the insulating layer includes at least one of a tunnel insulating layer, a blocking insulating layer, and a charge storing layer.

### Claim 51 (depends on 43)

The device as claimed in claim 43, wherein the insulating spacer has a cylindrical shape with an open end.

### Claim 52 (depends on 43)

The device as claimed in claim 43, wherein the semiconductor pattern has a cylindrical shape with an open end.

### Claim 53 (depends on 43)

The device as claim in claim 43, wherein the first structure includes three-dimensionally arranged memory devices.

### Claim 54

A three-dimensional semiconductor device, comprising:
a semiconductor substrate;
an underlying layer on the substrate;
a first structure on the underlying layer, the first structure including three-dimensionally arranged memory devices and having a first semiconductor pattern penetrating the first structure; and
a second structure on the first structure, the second structure including at least a conductive pattern and having a second semiconductor pattern penetrating the second structure,
wherein the first structure and the second structure electrically is connected to each other via the first semiconductor pattern and the second semiconductor pattern, and a lower end of the second semiconductor pattern is disposed on and proximal to an upper end of the first semiconductor pattern, and a lower end of the first semiconductor pattern is in contact with the semiconductor substrate and an upper end of the second semiconductor pattern is electrically connected to a bit line.

### Claim 55 (depends on 54)

The device as claimed in claim 54, wherein the underlying layer is formed of aluminum oxide.

### Claim 56 (depends on 54)

The device as claimed in claim 54, further comprising a pad pattern interposed between the first structure and the second structure.