# US 2018/0323207 A1 · Semiconductor device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0323207 A1 - Document ID: US20180323207A1 - Status: Published application - Kind: A1 - Application number: 15/850,592 - Filed: 2017-12-21 - Published: 2018-11-08 - Earliest claimed: 2017-05-04 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sung Bo SHIM; Jung Dal CHOI - Web page: https://patentgrep.com/patent/US20180323207A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/30: Power supply circuits - G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells} - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 88/00: Three-dimensional [3D] integrated devices - H10D 88/01: {Manufacture or treatment} - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 72/90: Bond pads, in general - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate. ## Claims ### Claim 1 A semiconductor device comprising: a first substrate; a second substrate disposed over the first, substrate; a stack with stacked memory cells disposed on the second substrate; and a discharge contact structure electrically coupling the second substrate with the first substrate, wherein charges in the second substrate are discharged to the first substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the discharge contact structure comprises one or more contact plugs that contact with a front surface of the first substrate and a rear surface of the second substrate. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the stack comprises channel structures passing through the stack, and the contact plugs are disposed between the channel structures. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first substrate comprises a junction that contacts with the discharge contact structure. ### Claim 5 The semiconductor device according to claim: further comprising: a peripheral circuit formed on the first substrate. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein each of the first substrate and the second substrate is a semiconductor substrate. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the discharge contact structure is disposed below the memory cells. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising: an erase contact structure electrically coupling the second substrate with the first substrate, wherein an erase bias is applied to a well region of the second substrate. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the discharge contact structure comprises one or more contact plugs that contact with a front surface of the first substrate and a rear surface of the second substrate, wherein the discharge contact structure is disposed below the memory cells so that the contact plugs become a passage for discharging charges of the second substrate and a passage for applying an erase bias during an erase operation. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the stack includes conductive layers and insulating layers that are alternately stacked. ### Claim 11 (depends on 8) The semiconductor device according to claim 8, wherein the erase contact structure comprises: a first contact plug electrically coupled with a front surface of the second substrate; a second contact plug electrically coupled with the front surface of the first substrate; and a line electrically coupling the first contact plug with the second contact plug. ### Claim 12 (depends on 8) The semiconductor device according to claim 8, wherein the stack comprises a cell region including the memory cells, and a contact region patterned in a stepped shape, and wherein the discharge contact structure is disposed below the cell region, and the erase contact structure is disposed below the contact region. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the erase contact structure includes one or more contact plugs so that the contact plugs contact with a front surface of the first substrate and a rear surface of the second substrate. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the second substrate comprises a well region, and an erase bias is applied to the well region of the second substrate through the discharge contact structure. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the stack comprises a cell region including the memory cells, and a contact region patterned in a stepped shape, and wherein the discharge contact structure is disposed below the contact region. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, further comprising: an erase contact structure electrically coupling the second substrate with the first substrate, wherein an erase bias is applied to a well region of the second substrate. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the erase contact structure comprises: a first contact plug electrically coupled with a front surface of the second substrate and disposed over the discharge contact structure; a second contact plug electrically coupled with a front surface of the first substrate; and a line electrically coupling the first contact plug with the second contact plug. ### Claim 18 (depends on 1) The semiconductor device according to claim 1, wherein the discharge contact structure comprises: a first contact plug electrically coupled with a front surface of the first substrate; a second contact plug electrically coupled with a rear surface of the second substrate; and a line electrically coupling the first contact plug with the second contact plug.