# US 2018/0323200 A1 · Memory Arrays

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0323200 A1
- Document ID: US20180323200A1
- Status: Published application
- Kind: A1
- Application number: 15/973,707
- Filed: 2018-05-08
- Published: 2018-11-08
- Earliest claimed: 2017-05-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sanh D. Tang; Martin C. Roberts
- Web page: https://patentgrep.com/patent/US20180323200A1

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/036: {the capacitor extending under the transistor}
- H10B 12/05: {Making the transistor}
- H10B 12/48: {Data lines or contacts therefor}
- H10B 53/30: characterised by the memory core region
- H10D 1/692: {Electrodes}
- H10D 1/714: {having horizontal extensions}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/43: Layouts of interconnections
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.

## Claims

### Claim 1

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising a transistor and a capacitor, one of (a) a channel region of the transistor, or (h) a pair of electrodes of the capacitor, being directly above the other of (a) and (b).

### Claim 2 (depends on 1)

The array of claim 1 wherein the channel region is directly above the pair of electrodes.

### Claim 3 (depends on 1)

The array of claim 1 wherein the pair of electrodes is directly above the channel region.

### Claim 4 (depends on 1)

The array of claim 1 wherein the transistor comprises first and second source/drain regions neither of which is directly above the other.

### Claim 5 (depends on 1)

The array of claim 1 wherein the transistor comprises first and second source/drain regions one of which is above the other.

### Claim 6 (depends on 5)

The array of claim 5 wherein neither of the first and second source/drain regions is directly above the other.

### Claim 7 (depends on 1)

The array of claim 1 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through.

### Claim 8 (depends on 1)

The array of claim 1 wherein the transistor comprises first and second source/drain regions having the channel region there-between, the first and second source/drain regions and the channel region collectively comprising opposing C-like shapes that face one another in a straight-line vertical cross-section.

### Claim 9 (depends on 1)

The array of claim 1 wherein at least one electrode of the pair comprises opposing C-like shapes that face one another in a straight-line vertical cross-section.

### Claim 10 (depends on 1)

The array of claim 1 rein the channel region comprises an annulus a straight-line horizontal cross-section.

### Claim 11 (depends on 1)

The array of claim 1 wherein at least one of the pair of electrodes comprises an annulus in a straight-line horizontal cross-section.

### Claim 12 (depends on 1)

The array of claim 1 wherein the transistor comprises a gate, the gate comprising an annulus in a straight-line horizontal cross-section.

### Claim 13 (depends on 12)

The array of claim 12 wherein a plurality of the gates in individual of the tiers of memory cells are directly electrically coupled to one another along a conductive line, the annuli of immediately-laterally-adjacent of the gates overlapping one another in the line.

### Claim 14

A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another; and
one of (a) the channel region of the transistor, or (b) the first and second electrodes of the capacitor, being directly above the other of (a) and (b); and
a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure.

### Claim 15 (depends on 14)

The array of claim 14 wherein the sense-line structure is directly electrically coupled to a horizontal longitudinally-elongated sense line that is above or below the vertically-alternating tiers.

### Claim 16 (depends on 14)

The array of claim 14 wherein the sense-line structure comprises a pillar.

### Claim 17

A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; and
one of (a) the channel region of the transistor, or (b) the first and second electrodes of the capacitor, being directly above the other of (a) and (b);
a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure; and
a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers.

### Claim 18 (depends on 17)

The array of claim 17 wherein the sense-line structure comprises a pillar.

### Claim 19 (depends on 17)

The array of claim 17 comprising at least one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the individual second electrodes of the individual capacitors that are in different memory cell tiers being electrically coupled to the at least one more elevationally-extending capacitor-electrode structure.

### Claim 20 (depends on 19)

The array of claim 19 comprising more than one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers.

### Claim 21 (depends on 20)

The array of claim 20 wherein the capacitor-electrode structures are circumferentially spaced about the first electrode.

### Claim 22 (depends on 21)

The array of claim 21 wherein the capacitor-electrode structures total six in number.

### Claim 23 (depends on 17)

The array of claim 17 wherein the capacitor-electrode structure is directly electrically coupled to a horizontally-elongated capacitor-electrode construction that is above or below the vertically-alternating tiers.

### Claim 24

A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; and
one of (a) the channel region of the transistor, or (b) the first and second electrodes of the capacitor, being directly above the other of (a) and (b);
a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure; and
a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure.

### Claim 25 (depends on 24)

The array of claim 24 comprising at least one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the individual second electrodes of the individual capacitors being electrically coupled to the at least one more elevationally-extending capacitor-electrode structure.

### Claim 26 (depends on 25)

The array of claim 25 comprising more than one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the capacitor-electrode structures being circumferentially spaced about the first electrode.

### Claim 27 (depends on 24)

The array of claim 24 wherein the gate comprises an annulus in a straight-line horizontal cross-section, a plurality of the gates in individual of the tiers of memory cells being directly electrically coupled to one another along a conductive line, the annuli of immediately-laterally-adjacent of the gates overlapping one another in the line.